BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Warsaw BEGIN:DAYLIGHT DTSTART:20150329T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20151025T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20150915T133522Z UID:9D27BD0C-5BAE-11E5-BFEA-0050568D7F66 DTSTART;TZID=Europe/Warsaw:20151012T090000 DTEND;TZID=Europe/Warsaw:20151013T170000 DESCRIPTION:During IEEE SSCS Chapter Poland Meeting Prof. Willy Sansen will give 2-day course on "Circuits with resistor and capacitor cancellation: design techniques to enhance high-frequency performance without increased power consumption".\n\nSpeaker(s): Willy Sansen\, \, Willy Sansen\, \n\nAg enda: \nMonday\, Oct. 12th\, 2015\, 9.00-10.30\, building B1\, room 121\n\ n1.1 Minimum-power amplifying stages\n\nSingle-transistor stages determine the performance for high-frequency blocks such as LNA’s and VCO’s. Mo reover they determine the gain\, which can be realized in nanometer CMOS t ransistor stages. The gain\, input and output impedance is analyzed of the three single-transistor stages i.e. the amplifier\, the source follower a nd the cascode. In addition the current consumption is minimized of the am plifying stage using EKV/BSIM6 models.\n\nMonday\, Oct. 12th\, 2015\, 11.0 0-12.30\, building B1\, room 121\n\n1.2 Differential amplifying blocks wit h positive feedback\n\nPractical designs are built up by means of differen tial pairs\, current sources and two-transistor cascodes. They are analyze d in details followed by fully-differential voltage and current amplifiers . Positive feedback is added as well to enhance both the Gain and the Gain -Bandwidth. Design procedures are discussed in all regions of operations ( from weak to strong inversion and velocity saturation).\n\nMonday\, Oct. 1 2th\, 2015\, 13.30-15.00\, building B1\, room 121\n\n1.3 High-frequency an d RF design techniques\n\nReal high-frequency performance can be reached u p to fT/3 even if all parasitic components are included. In addition feedf orward and pole-zero compensation schemes can be adopted to extend the fre quency range. Many examples are given and discussed.\n\nMonday\, Oct. 12th \, 2015\, 15.30-17.00\, building B1\, room 121\n\n1.4 Examples of low-nois e design\n\nLow-noise design techniques are applied to amplifier configura tions\, filters and LNA’s. Indeed wireless receivers all start with a LN A (Low-noise amplifier) to provide limited gain but with low noise and dis tortion. The most recent ones are all wide-band\, and use both noise and d istortion cancellation\, which yields higher FOM’s than hitherto possibl e.\n\nTuesday\, Oct. 13th\, 2015\, 9.00-10.30\, building B1\, room 121\n\n 2.1 Compensation techniques in operational amplifiers\n\nTwo-stage operati onal amplifiers in unity-gain configuration\, suffer from peaking unless a compensation capacitance is added\, or the current is increased in the se cond stage. These stability conditions are examined followed by three tech niques to get rid of the positive zero. These design plans are extended to three-stage amplifiers with nested Miller compensation.\n\nTuesday\, Oct. 13th\, 2015\, 11.00-12.30\n\n2.2 Most-important opamp configurations\n\nI n practice only a few amplifier configurations are used. Examples are the symmetrical amplifier\, the folded-cascode and the Miller OTA amplifier. I n this presentation\, all of them are optimized with respect to power cons umption\, high-speed capability and noise. The compromises are discussed i n detail and a comparison is provided. In addition\, some specific design techniques such as negative resistors\, are reviewed to enhance performanc e.\n\nTuesday\, Oct. 13th\, 2015\, 13.30-15.00\, building B1\, room 121\n\ n2.3 Design of multistage operational amplifiers\n\nTwo-stage amplifiers m ay not provide sufficient gain and or frequency performance in nanometer C MOS technologies. This is why three-stage amplifiers have become necessary . This is also true for most power amplifiers in which two preceding stage s are required for high gain. The stability is analyzed of such amplifiers . It is shown that three-stage amplifiers can provide tracking pole-zero c ompensation\, which results in lower power consumption than a two-stage am plifier with similar performance.\n\nTuesday\, Oct. 13th\, 2015\, 15.30-17 .00\, building B1\, room 121\n\n2.4 Opamps\, Gm-block or Inverters for fil ters\n\nOperational amplifiers have been the backbone of most amplifiers a nd filters in communication applications and ADCs. They are in competition with Gm blocks for higher frequencies despite their higher linearity. Bot h of them are now gradually being replaced by CMOS inverters. This present ation focuses on the merits and advantages of all three of them.\n\nRoom: 121\, Bldg: B1\, AGH University of Science and Technology\, Av. Mickiewicz a 30\, Cracow\, Malopolskie\, Poland\, 30-059 LOCATION:Room: 121\, Bldg: B1\, AGH University of Science and Technology\, Av. Mickiewicza 30\, Cracow\, Malopolskie\, Poland\, 30-059 ORGANIZER:kasinski@agh.edu.pl SEQUENCE:0 SUMMARY:IEEE SSCS Chapter Poland Meeting - Course on Microelectronics by Wi lly Sansen URL;VALUE=URI:https://events.vtools.ieee.org/m/36069 X-ALT-DESC:Description: <br /><p>During IEEE SSCS Chapter Poland Meeting Pr of. Willy Sansen will give 2-day course on "<em>Circuits with resistor and capacitor cancellation: design techniques to enhance high-frequency perfo rmance without increased power consumption</em>".</p><br /><br />Agenda: < br /><p><strong>Monday\, Oct. 12th\, 2015\, 9.00-10.30\, building B1\, roo m 121</strong></p>\n<p><strong>1.1&nbsp\;&nbsp\;</strong><strong>Minimum-p ower amplifying stages</strong></p>\n<p>Single-transistor stages determine the performance for high-frequency blocks such as LNA&rsquo\;s and VCO&rs quo\;s. Moreover they determine the gain\, which can be realized in nanome ter CMOS transistor stages. The gain\, input and output impedance is analy zed of the three single-transistor stages i.e. the amplifier\, the source follower and the cascode.&nbsp\; In addition the current consumption is mi nimized of the amplifying stage using EKV/BSIM6 models.</p>\n<p><strong>&n bsp\;</strong></p>\n<p><strong>Monday\, Oct. 12th\, 2015\, 11.00-12.30\,&n bsp\;<strong>building B1\, room 121</strong></strong></p>\n<p><strong>1.2& nbsp\;&nbsp\;</strong><strong>Differential amplifying blocks with positive feedback</strong></p>\n<p>Practical designs are built up by means of diff erential pairs\, current sources and two-transistor cascodes. They are ana lyzed in details followed by fully-differential voltage and current amplif iers. Positive feedback is added as well to enhance both the Gain and the Gain-Bandwidth. Design procedures are discussed in all regions of operatio ns (from weak to strong inversion and velocity saturation).</p>\n<p><stron g>&nbsp\;</strong></p>\n<p><strong>Monday\, Oct. 12th\, 2015\, 13.30-15.00 \,&nbsp\;<strong>building B1\, room 121</strong></strong></p>\n<p><strong> 1.3&nbsp\;&nbsp\;</strong><strong>High-frequency and RF design techniques< /strong></p>\n<p>Real high-frequency performance can be reached up to fT/3 even if all parasitic components are included. In addition feedforward an d pole-zero compensation schemes can be adopted to extend the frequency ra nge. Many examples are given and discussed.</p>\n<p><strong>&nbsp\;</stron g></p>\n<p><strong>Monday\, Oct. 12th\, 2015\, 15.30-17.00\,&nbsp\;<strong >building B1\, room 121</strong></strong></p>\n<p><strong>1.4&nbsp\;&nbsp\ ;</strong><strong>Examples of low-noise design</strong></p>\n<p>Low-noise design techniques are applied to amplifier configurations\, filters and LN A&rsquo\;s. Indeed wireless receivers all start with a LNA (Low-noise ampl ifier) to provide limited gain but with low noise and distortion. The most recent ones are all wide-band\, and use both noise and distortion cancell ation\, which yields higher FOM&rsquo\;s than hitherto possible.</p>\n<p>< strong>&nbsp\;</strong></p>\n<p><strong>Tuesday\, Oct. 13th\, 2015\, 9.00- 10.30\,&nbsp\;<strong>building B1\, room 121</strong></strong></p>\n<p><st rong>2.1 Compensation techniques in operational amplifiers</strong></p>\n< p>Two-stage operational amplifiers in unity-gain configuration\, suffer fr om peaking unless a compensation capacitance is added\, or the current is increased in the second stage. These stability conditions are examined fol lowed by three techniques to get rid of the positive zero. These design pl ans are extended to three-stage amplifiers with nested Miller compensation .</p>\n<p><strong>&nbsp\;</strong></p>\n<p><strong>Tuesday\, Oct. 13th\, 2 015\, 11.00-12.30</strong></p>\n<p><strong>2.2 Most-important opamp config urations</strong></p>\n<p>In practice only a few amplifier configurations are used. Examples are the symmetrical amplifier\, the folded-cascode and the Miller OTA amplifier. In this presentation\, all of them are optimized with respect to power consumption\, high-speed capability and noise. The compromises are discussed in detail and a comparison is provided. In addit ion\, some specific design techniques such as negative resistors\, are rev iewed to enhance performance.</p>\n<p><strong>&nbsp\;</strong></p>\n<p><st rong>Tuesday\, Oct. 13th\, 2015\, 13.30-15.00\,&nbsp\;<strong>building B1\ , room 121</strong></strong></p>\n<p><strong>2.3 Design of multistage oper ational amplifiers</strong></p>\n<p>Two-stage amplifiers may not provide s ufficient gain and or frequency performance in nanometer CMOS technologies . This is why three-stage amplifiers have become necessary. This is also t rue for most power amplifiers in which two preceding stages are required f or high gain. The stability is analyzed of such amplifiers. It is shown th at three-stage amplifiers can provide tracking pole-zero compensation\, wh ich results in lower power consumption than a two-stage amplifier with sim ilar performance.</p>\n<p><strong>&nbsp\;</strong></p>\n<p><strong>Tuesday \, Oct. 13th\, 2015\, 15.30-17.00\,&nbsp\;<strong>building B1\, room 121</ strong></strong></p>\n<p><strong>2.4 Opamps\, Gm-block or Inverters for fi lters</strong></p>\n<p>Operational amplifiers have been the backbone of mo st amplifiers and filters in communication applications and ADCs.&nbsp\; T hey are in competition with Gm blocks for higher frequencies despite their higher linearity. Both of them are now gradually being replaced by CMOS i nverters. This presentation focuses on the merits and advantages of all th ree of them.</p> END:VEVENT END:VCALENDAR