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DTSTAMP:20230528T150123Z
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DESCRIPTION:The demand for high-speed\, low-power analog-to-digital convert
 ers (ADCs) for high-speed wireline transceivers and mmWave radios continue
 s to grow unabated\, driven in part by advances in DSP-based architectures
  and technology-scaling benefits in digital circuits. Recent works on high
 -speed ADCs operating at > 10 GHz with 6 to 8 bits of resolution have made
  tremendous progress\, but significant challenges remain. This talk discus
 ses techniques to achieve simultaneous high speed and high power efficienc
 y by using the time-interleaved successive-approximation-register (SAR) ar
 chitecture. We present “constant-matching scaling” and “grouped capa
 citors” for the digital-to-analog-converter (DAC) to aggressively reduce
  the capacitance and increase the speed. The ADC also demonstrates a “du
 al-path” bootstrapped switch to increase the sampling spurious-free dyna
 mic range (SFDR). Employing the above and other low-power\, high-speed tec
 hniques\, the proposed SAR ADC obtains a single-channel speed of 1.25-GHz 
 without the need for pipelining. The ADC uses only 8X time-interleaving to
  achieve an overall sampling rate of 10 GHz and a signal-to-noise-and-dist
 ortion ratio (SNDR) of 36.9 dB at Nyquist while consuming 21 mW.\n\nSpeake
 r(s): Shiuh-hua Wood Chiang\, \n\nRoom: 240\, Bldg: Electrical Engineering
 \, 94 Brett Road\, Piscataway\, New Jersey\, United States\, 08854
LOCATION:Room: 240\, Bldg: Electrical Engineering\, 94 Brett Road\, Piscata
 way\, New Jersey\, United States\, 08854
ORGANIZER:ctm.wu@rutgers.edu
SEQUENCE:10
SUMMARY:Techniques for High-Performance Successive-Approximation-Register A
 DCs
URL;VALUE=URI:https://events.vtools.ieee.org/m/361551
X-ALT-DESC:Description: <br /><p>The demand for high-speed\, low-power anal
 og-to-digital converters (ADCs) for high-speed wireline transceivers and m
 mWave radios continues to grow unabated\, driven in part by advances in DS
 P-based architectures and technology-scaling benefits in digital circuits.
  Recent works on high-speed ADCs operating at &gt\; 10 GHz with 6 to 8 bit
 s of resolution have made tremendous progress\, but significant challenges
  remain. This talk discusses techniques to achieve simultaneous high speed
  and high power efficiency by using the time-interleaved successive-approx
 imation-register (SAR) architecture. We present &ldquo\;constant-matching 
 scaling&rdquo\; and &ldquo\;grouped capacitors&rdquo\; for the digital-to-
 analog-converter (DAC) to aggressively reduce the capacitance and increase
  the speed. The ADC also demonstrates a &ldquo\;dual-path&rdquo\; bootstra
 pped switch to increase the sampling spurious-free dynamic range (SFDR). E
 mploying the above and other low-power\, high-speed techniques\, the propo
 sed SAR ADC obtains a single-channel speed of 1.25-GHz without the need fo
 r pipelining. The ADC uses only 8X time-interleaving to achieve an overall
  sampling rate of 10 GHz and a signal-to-noise-and-distortion ratio (SNDR)
  of 36.9 dB at Nyquist while consuming 21 mW.</p>
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