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DTSTART:20380119T001407
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DTSTART:20150308T010000
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DTSTAMP:20230628T223745Z
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DTSTART;TZID=America/Montevideo:20230620T083000
DTEND;TZID=America/Montevideo:20230620T100000
DESCRIPTION:Data analytics involves the discovery of patterns and complex r
 elations in data to assist with effective decision-making. Such analytics 
 are applied on a variety of data forms such as video streams\, financial d
 ata\, social media messages\, and sensor information from smart homes and 
 personal health monitoring devices. However\, data analytics is becoming e
 xceedingly challenging as the generated volume of data is increasing expon
 entially. Co-design across the stack from materials to architectures will 
 be vital to addressing crosscutting challenges posed by the enormity of da
 ta that needs to be processed. This talk will showcase such optimization t
 argeted at visual analytic applications such as Deep Neural networks\, gra
 ph analytics and query support.\n\nFirst\, I will present a Look-Up Table 
 (LUT) based Processing-In-Memory (PIM) technique with the potential for ru
 nning Neural Network inference tasks. The proposed LUT-based PIM methodolo
 gy exploits substantial parallelism using look-up tables that preserve the
  bit-cell and peripherals of the existing SRAM monolithic arrays in proces
 sor caches. Next\, I will present GaaS-X\, a graph analytics accelerator t
 hat inherently supports sparse graph data representations using in-situ co
 mpute-enabled crossbar memory architectures. The proposed design alleviate
 s the overheads of redundant writes\, sparse to dense conversions\, and re
 dundant computations on the invalid edges that are present in other state-
 of-the-art crossbar-based PIM accelerators. Finally\, I will present an in
 -SSD key-value database that uses the embedded CPU core\, and DRAM memory 
 on the SSD to support various queries with predicates and reduce the data 
 movement between SSD and host processor significantly.\n\nCo-sponsored by:
  Grupo de Microelectrónica\, Facultad de Ingeniería\, Universidad de la 
 República\n\nSpeaker(s): Vijaykrishnan Narayanan\n\nRoom: Laboratorio de 
 Software del IIE\, Bldg: Facultad de Ingeniería\, Julio Herrera y Reissig
  565\, Montevideo\, Montevideo\, Uruguay
LOCATION:Room: Laboratorio de Software del IIE\, Bldg: Facultad de Ingenier
 ía\, Julio Herrera y Reissig 565\, Montevideo\, Montevideo\, Uruguay
ORGANIZER:msiniscalchi@fing.edu.uy
SEQUENCE:14
SUMMARY:Accelerating Visual Analytics across the Memory and Storage Stack
URL;VALUE=URI:https://events.vtools.ieee.org/m/364189
X-ALT-DESC:Description: <br /><p>Data analytics involves the discovery of p
 atterns and complex relations in data to assist with effective decision-m
 aking. Such analytics are applied on a variety of data forms such as video
  streams\, financial data\, social media messages\, and sensor information
  from smart homes and personal health monitoring devices. However\, data a
 nalytics is becoming exceedingly challenging as the generated volume of da
 ta is increasing exponentially. Co-design across the stack from materials 
 to architectures will be vital to addressing crosscutting challenges pose
 d by the enormity of data that needs to be processed. This talk will showc
 ase such optimization targeted at visual analytic applications such as Dee
 p Neural networks\, graph analytics and query support.</p>\n<p>First\, I w
 ill present a Look-Up Table (LUT) based Processing-In-Memory (PIM) techniq
 ue with the potential for running Neural Network inference tasks. &nbsp\;T
 he proposed LUT-based PIM methodology exploits substantial parallelism usi
 ng look-up tables that preserve the bit-cell and peripherals of the existi
 ng SRAM monolithic arrays in processor caches. Next\, I will present GaaS-
 X\, a graph analytics accelerator that inherently supports sparse graph da
 ta representations using in-situ compute-enabled crossbar memory architect
 ures. The proposed design alleviates the overheads of redundant writes\, s
 parse to dense conversions\, and redundant computations on the invalid edg
 es that are present in other state-of-the-art crossbar-based PIM accelerat
 ors. Finally\, I will present an in-SSD key-value database that uses the e
 mbedded CPU core\, and DRAM memory on the SSD to support various queries w
 ith predicates and reduce the data movement between SSD and host processor
  significantly.</p>
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