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CALSCALE:GREGORIAN
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RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11
TZNAME:EST
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DTSTAMP:20230729T020846Z
UID:065CEEB6-3015-47D2-A7FC-E25F9250AA62
DTSTART;TZID=America/New_York:20230727T183000
DTEND;TZID=America/New_York:20230727T200000
DESCRIPTION:IEEE Electronic Packaging Society Distinguished Lecture\n\nWith
  the increasing demands for higher signal speeds coupled with the need for
  decreasing feature sizes\, signal integrity effects such as delay\, disto
 rtion\, reflections\, crosstalk\, ground bounce and electromagnetic interf
 erence have become the dominant factors limiting the performance of high-s
 peed systems. These effects can be diverse and can seriously impact the de
 sign performance at all hierarchical levels including integrated circuits\
 , printed circuit boards\, multi-chip modules and backplanes. If not consi
 dered during the design stage\, signal and power integrity effects can cau
 se failed designs. Since extra iterations in the design cycle are costly\,
  accurate prediction of these effects is a necessity in high-speed designs
 . Consequently\, preserving signal integrity has become one of the most ch
 allenging tasks facing designers of modern multifunction and miniature ele
 ctronic circuits and systems. This talk provides a comprehensive approach 
 for understanding the multidisciplinary problem of signal and power integr
 ity: issues/modeling/analysis in high-speed designs.\n\nSpeaker(s): Prof. 
 Ram Achar\n\nAgenda: \n6:30 PM : Announcements and Introduction of Speaker
 \n\n6:40 PM - Talk\n\n7:20 PM - Q and A\n\nRoom: Meeting Room\, Bldg: Patr
 ick Henry Library\, 101 Maple Ave E\, Vienna\, Virginia\, United States\, 
 Virtual: https://events.vtools.ieee.org/m/365848
LOCATION:Room: Meeting Room\, Bldg: Patrick Henry Library\, 101 Maple Ave E
 \, Vienna\, Virginia\, United States\, Virtual: https://events.vtools.ieee
 .org/m/365848
ORGANIZER:tonyguoxy@gmail.com
SEQUENCE:24
SUMMARY:Emerging Challenges of Signal Integrity Issues and High-Speed Inter
 connects
URL;VALUE=URI:https://events.vtools.ieee.org/m/365848
X-ALT-DESC:Description: <br /><p>IEEE Electronic Packaging Society Distingu
 ished Lecture</p>\n<p>With the increasing demands for higher signal speeds
  coupled with the need for decreasing feature sizes\, signal integrity eff
 ects such as delay\, distortion\, reflections\, crosstalk\, ground bounce 
 and electromagnetic interference have become the dominant factors limiting
  the performance of high-speed systems. These effects can be diverse and c
 an seriously impact the design performance at all hierarchical levels incl
 uding integrated circuits\, printed circuit boards\, multi-chip modules an
 d backplanes. If not considered during the design stage\, signal and power
  integrity effects can cause failed designs. Since extra iterations in the
  design cycle are costly\, accurate prediction of these effects is a neces
 sity in high-speed designs. Consequently\, preserving signal integrity has
  become one of the most challenging tasks facing designers of modern multi
 function and miniature electronic circuits and systems. This talk provides
  a comprehensive approach for understanding the multidisciplinary problem 
 of signal and power integrity: issues/modeling/analysis in high-speed desi
 gns.</p><br /><br />Agenda: <br /><p>6:30 PM : Announcements and Introduct
 ion of Speaker</p>\n<p>6:40 PM - Talk</p>\n<p>7:20 PM - Q and A</p>
END:VEVENT
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