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DTSTAMP:20230821T024057Z
UID:B03A6E1A-512A-4843-801E-55FE35580919
DTSTART;TZID=America/Los_Angeles:20230817T180000
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DESCRIPTION:Cell-based\, synthesizable mixed-signal circuits such as ADPLLs
 \, ADCs\, and LDOs are gaining significant traction. This is fueled by the
  exponentially increasing number of DRC rules in advanced nodes\, added re
 strictions on custom layout\, and overall increase in design time for full
 -custom\, analog designs. This talk focuses on a different technique for a
 nalog design automation that borrows from the digital design flow. I will 
 show how we can describe ADPLLs and LDOs using a combination of standard c
 ells\, and a small number of auxiliary cells. These aux cells are no large
 r than a D-flipflop\, and are drawn on the standard cell grid. This means 
 they can be included in existing digital synthesis and automatic place & r
 oute (APR) flows\, leveraging these very powerful commercial tools. I will
  present our innovations at the architecture level\, and on how we drive t
 he EDA tools\, in order to improve performance. Examples and measurement r
 esults will be shown\, from fabricated ADPLLs and LDOs in TSMC 65nm and GF
  12nm\, demonstrating the ease of porting these designs across processes.\
 n\nSpeaker(s): \, David Wentzloff\n\nVirtual: https://events.vtools.ieee.o
 rg/m/369117
LOCATION:Virtual: https://events.vtools.ieee.org/m/369117
ORGANIZER:geochen1@yahoo.com
SEQUENCE:35
SUMMARY:Cell-Based Design Automation for Mixed-Signal Circuits
URL;VALUE=URI:https://events.vtools.ieee.org/m/369117
X-ALT-DESC:Description: <br /><div><span style="font-size: medium\;">Cell-b
 ased\, synthesizable mixed-signal circuits such as ADPLLs\, ADCs\, and LDO
 s are gaining significant traction. This is fueled by the exponentially in
 creasing number of DRC rules in advanced nodes\, added restrictions on cus
 tom layout\, and overall increase in design time for full-custom\, analog 
 designs. This talk focuses on a different technique for analog design auto
 mation that borrows from the digital design flow. I will show how we can d
 escribe ADPLLs and LDOs using a combination of standard cells\, and a smal
 l number of auxiliary cells. These aux cells are no larger than a D-flipfl
 op\, and are drawn on the standard cell grid. This means they can be inclu
 ded in existing digital synthesis and automatic place &amp\; route (APR) f
 lows\, leveraging these very powerful commercial tools. I will present our
  innovations at the architecture level\, and on how we drive the EDA tools
 \, in order to improve performance. Examples and measurement results will 
 be shown\, from fabricated ADPLLs and LDOs in TSMC 65nm and GF 12nm\, demo
 nstrating the ease of porting these designs across processes.</span></div>
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