BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20230312T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20231105T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20230922T123250Z UID:94546AA9-E9E9-40F9-8B9F-3EC4E5ACC885 DTSTART;TZID=America/New_York:20230921T193000 DTEND;TZID=America/New_York:20230921T210000 DESCRIPTION:The advancement of Artificial Intelligence (AI) and its rapid d eployment on a broad spectrum of platforms relies on both design quality a nd design efficiency of circuits\, systems\, and algorithms. Moreover\, se curity and robustness concerns arise at both hardware and software levels in some critical applications of AI models. Cross-layer optimization becom es essential to achieve these goals. In this talk\, we first introduce cir cuit-level innovations for emerging AI models and devices\, including the popular processing-in-memory (PIM) computing primitives centered on variou s new types of nanodevices. After that\, we discuss efficient architecture design atop these innovations\, such as multiplier array\, systolic array \, PIM-based deep neural network (DNN)\, and spiking neural network (SNN) pipelines. Then we present hardware-friendly model compression techniques to optimize the quality-efficiency trade-off on AI models. We also introdu ce several efficient distributed learning frameworks that enable the scala bility of AI systems. Finally\, we show some approaches to resolve the cha llenges introduced by the imperfect characteristics of semiconductor devic es and the security concerns in real-world systems. We hope our talk will offer the audience a comprehensive overview of a full-stack design and opt imization of efficient AI circuits and systems (AI-CAS) solutions.\n\nSpea ker(s): Dr. Yiran Chen\, \n\nAgenda: \n730 PM - login to google meet and s tart of presentation\n\n900 PM - end of event\n\nVirtual: https://events.v tools.ieee.org/m/369615 LOCATION:Virtual: https://events.vtools.ieee.org/m/369615 ORGANIZER:jeff.dulzo@gmail.com SEQUENCE:19 SUMMARY:Efficient and Robust AI Circuits and System (AI-CAS) through Cross- Layer Optimization URL;VALUE=URI:https://events.vtools.ieee.org/m/369615 X-ALT-DESC:Description: <br /><p>The advancement of Artificial Intelligence (AI) and its rapid deployment on a broad spectrum of platforms relies on both design quality and design efficiency of circuits\, systems\, and algo rithms. Moreover\, security and robustness concerns arise at both hardware and software levels in some critical applications of AI models. Cross-lay er optimization becomes essential to achieve these goals. In this talk\, w e first introduce circuit-level innovations for emerging AI models and dev ices\, including the popular processing-in-memory (PIM) computing primitiv es centered on various new types of nanodevices. After that\, we discuss e fficient architecture design atop these innovations\, such as multiplier a rray\, systolic array\, PIM-based deep neural network (DNN)\, and spiking neural network (SNN) pipelines. Then we present hardware-friendly model co mpression techniques to optimize the quality-efficiency trade-off on AI mo dels. We also introduce several efficient distributed learning frameworks that enable the scalability of AI systems. Finally\, we show some approach es to resolve the challenges introduced by the imperfect characteristics o f semiconductor devices and the security concerns in real-world systems. W e hope our talk will offer the audience a comprehensive overview of a full -stack design and optimization of efficient AI circuits and systems (AI-CA S) solutions.</p><br /><br />Agenda: <br /><div class="mx-auto break-words word-wrap prose font-serif">\n<p>730 PM - login to google meet and start of presentation</p>\n<p>900 PM - end of event</p>\n</div>\n<p>&nbsp\;</p> END:VEVENT END:VCALENDAR