BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Shanghai BEGIN:STANDARD DTSTART:19910915T010000 TZOFFSETFROM:+0900 TZOFFSETTO:+0800 TZNAME:CST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20230824T033129Z UID:B8796C97-A0DA-4DAB-8D29-B6A65BBA66B3 DTSTART;TZID=Asia/Shanghai:20230822T100000 DTEND;TZID=Asia/Shanghai:20230822T110000 DESCRIPTION:Deep neural networks (DNNs) have achieved unprecedented success in a variety of applications. This success is from considerable demands f or data and computations\, which have spurred a pronounced interest in enh ancing DNN acceleration through parallelism and specialization. At the cor e of any DNN accelerator lies the communication network\, a pivotal compon ent that connects the numerous processing units and orchestrates the intri cate data movements resulting from the strategic arrangement of computatio ns. As contemporary metallic-based interconnects encounter escalating limi tations with the progression of system scaling\, we consider silicon photo nic interconnects a compelling alternative and investigate the consequent paradigm shift in communication network design and dataflow optimization.\ nThis talk describes our reevaluation of DNN characteristics within the co ntext of silicon photonics and three accelerator architectures that we hav e developed. The first architecture serves as a versatile platform for eas y integration of existing chip-scale DNN accelerators while the inter-chip let communication is supported by the adaptable silicon photonic interconn ects. In the second architecture\, silicon photonic interconnects are util ized to encompass both inter-chiplet and intra-chiplet communications\, ac companied by a complementary dataflow that spatially distributes independe nt multiplications while iteratively performing accumulations. The third a rchitecture facilitates multi-DNN execution through astute optimization of hardware resource allocation and one-hop communication support between ar bitrarily partitioned hardware resources.\n\nVirtual: https://events.vtool s.ieee.org/m/371214 LOCATION:Virtual: https://events.vtools.ieee.org/m/371214 ORGANIZER:cedar@ieee.org SEQUENCE:29 SUMMARY:Silicon Photonic Connectivity for Efficient Neural Network Accelera tion URL;VALUE=URI:https://events.vtools.ieee.org/m/371214 X-ALT-DESC:Description: <br /><p>Deep neural networks (DNNs) have achieved unprecedented success in a variety of applications. This success is from c onsiderable demands for data and computations\, which have spurred a prono unced interest in enhancing DNN acceleration through parallelism and speci alization. At the core of any DNN accelerator lies the communication netwo rk\, a pivotal component that connects the numerous processing units and o rchestrates the intricate data movements resulting from the strategic arra ngement of computations. As contemporary metallic-based interconnects enco unter escalating limitations with the progression of system scaling\, we c onsider silicon photonic interconnects a compelling alternative and invest igate the consequent paradigm shift in communication network design and da taflow optimization.<br />This talk describes our reevaluation of DNN char acteristics within the context of silicon photonics and three accelerator architectures that we have developed. The first architecture serves as a v ersatile platform for easy integration of existing chip-scale DNN accelera tors while the inter-chiplet communication is supported by the adaptable s ilicon photonic interconnects. In the second architecture\, silicon photon ic interconnects are utilized to encompass both inter-chiplet and intra-ch iplet communications\, accompanied by a complementary dataflow that spatia lly distributes independent multiplications while iteratively performing a ccumulations. The third architecture facilitates multi-DNN execution throu gh astute optimization of hardware resource allocation and one-hop communi cation support between arbitrarily partitioned hardware resources.</p> END:VEVENT END:VCALENDAR