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DTSTART:20231105T010000
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DTSTAMP:20231008T211720Z
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DTSTART;TZID=America/Chicago:20231005T180000
DTEND;TZID=America/Chicago:20231005T200000
DESCRIPTION:Doug Norton will give an overview of Austin-based InspireSemi
 ’s disruptive next generation Thunderbird compute accelerator for HPC&AI
  applications. This RISC-V based “supercomputer-cluster-on-a-chip” pac
 ks 1\,800 high performance CPU cores (all FP64 double-precision of their o
 wn design) onto a single SOC. For maximum/predictable performance and low 
 latency\, these CPU cores are all interconnected with their high bandwidth
 \, low-latency mesh interconnect that can connect up to 256 of Thunderbird
  chips. After 3 years of customer-driven development\, the chip is in fina
 l verification and will tape out at the end of September to TSMC. He will 
 also share why the team chose to leverage the open hardware RISC-V ISA vs.
  other options and provide an overview of some of the many initiatives in 
 the thriving RISC-V ecosystem.\n\nSpeaker(s): Doug Norton\n\nAgenda: \n6:0
 0 to 6:05 PM - Open for participants to enter and network.\n6:05 to 6:10 P
 M - IEEE LM and CTCN Business meeting and to introduce speaker.\n6:10 to 7
 :30 PM - Formal Program and Q&A.\n\nVirtual: https://events.vtools.ieee.or
 g/m/371510
LOCATION:Virtual: https://events.vtools.ieee.org/m/371510
ORGANIZER:kaiwong@ieee.org
SEQUENCE:49
SUMMARY:IEEE 9.21.2023 meeting moved to Oct 5\,2023: RISC-V Thunderbird SOC
  for HPC and AI Applications
URL;VALUE=URI:https://events.vtools.ieee.org/m/371510
X-ALT-DESC:Description: <br /><p>Doug Norton will give an overview of Austi
 n-based InspireSemi&rsquo\;s disruptive next generation Thunderbird comput
 e accelerator for HPC&amp\;AI applications. This RISC-V based &ldquo\;supe
 rcomputer-cluster-on-a-chip&rdquo\; packs 1\,800 high performance CPU core
 s (all FP64 double-precision of their own design) onto a single SOC. For m
 aximum/predictable performance and low latency\, these CPU cores are all i
 nterconnected with their high bandwidth\, low-latency mesh interconnect th
 at can connect up to 256 of Thunderbird chips. After 3 years of customer-d
 riven development\, the chip is in final verification and will tape out at
  the end of September to TSMC. He will also share why the team chose to le
 verage the open hardware RISC-V ISA vs. other options and provide an overv
 iew of some of the many initiatives in the thriving RISC-V ecosystem.</p><
 br /><br />Agenda: <br /><div dir="ltr" data-setdir="false">6:00 to 6:05 P
 M - Open for participants to enter and network.&nbsp\;</div>\n<div dir="lt
 r" data-setdir="false">6:05 to 6:10 PM - IEEE LM and CTCN Business meeting
  and to introduce speaker.</div>\n<div dir="ltr" data-setdir="false">6:10 
 to 7:30 PM - Formal Program and Q&amp\;A.&nbsp\;</div>
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