BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20240310T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20241103T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20240912T211109Z UID:F9CD6DEA-D536-401F-BF22-0AB1615A3054 DTSTART;TZID=America/New_York:20240916T180000 DTEND;TZID=America/New_York:20240916T193000 DESCRIPTION:This course has been canceled!\n\nCourse: 4 weeks\, 1 class wee kly\, evening. Rates are listed below. September 16\, 23\, 30 and October 7\, 2024.We can offer Continuing Education Units (CEU) and Professional De velopment Hours (PDH)\, if requested. A small fee may apply for the credit s.\n\nCourse Overview:\n\nField-programmable gate arrays (FPGAs) are versa tile integrated circuits that offer a flexible and reconfigurable hardware platform for implementing custom digital circuits\, particularly in appli cations requiring specialized architectures. Unlike application-specific i ntegrated circuits (ASICs)\, FPGAs can be programmed and reprogrammed afte r manufacturing using hardware description languages (HDLs)\, enabling rap id prototyping and iterative design processes. FPGAs can be found in telec ommunications\, signal processing\, aerospace\, and other scenarios demand ing high-performance computing\, parallel processing\, low-latency data pr ocessing\, and real-time operations. The newest trends include integrating FPGAs with systems on chip (SoCs) for implementing low-latency machine le arning (ML) and artificial intelligence.\n\nThis Advanced Digital Design c ourse is an intensive program designed to build upon foundational concepts in digital logic design and equip students with the skills needed to impl ement robust high-speed ML algorithms on an FPGA. Through a combination of theoretical lectures\, hands-on exercises\, and practical projects\, stud ents will explore advanced FPGA topics encompassing architectural consider ations\, signal integrity\, timing analysis\, and optimization techniques to achieve reliable and efficient high-speed designs. Additionally\, this course will encourage students to explore current research papers and real -world industry applications to foster a deeper appreciation for advanceme nts in state-of-the-art FPGA design.\n\nTarget audience: Students and prof essionals with a base knowledge of FPGA design looking to advance hardware design skills for developing complex customized circuits for efficient im plementation of ML.\n\nBenefits of attending:\n\n- Valuable professional d evelopment creating skills that lead to job offers\n- Reinforce and expand knowledge of VHDL and FPGA-specific design methodology.\n- Develop skills for implementing high-speed\, robust\, reliable circuits on FPGAs.\n- Gai n understanding of real-world industry applications of FPGAs and SoCs.\n\n Course Objectives: By the end of this course\, students will possess the e xpertise needed to tackle complex high-speed hardware design challenges us ing FPGAs. They will be well-prepared to contribute to cutting-edge resear ch\, industry projects\, and advancements in areas such as telecommunicati ons\, data centers\, embedded systems\, and high-performance computing.\n\ nPrerequisites:\n\n- Understanding of digital logic design principles and methodology (e.g.\, Boolean algebra\, finite state machines\, data path el ements)\n- Familiarity with VHDL programming (or Verilog)\n- Experience wi th FPGA development boards and tools (e.g.\, Vivado)\n\nDetailed Course Ou tline:\n\n- Review of Digital Logic Design and FPGA Programming\n- Boolean algebra\, combinational and sequential circuits\, finite state machines\n - FPGA\, SoC\, and SoM architectures and toolchains\n- VHDL programming te chniques and design methodology\n- Writing effective testbenches\, RTL sim ulation in Vivado\n- Introduction to ML algorithms and FPGA-specific optim ization strategies\n\n- High-throughput Communication on FPGAs\n- Pipelini ng and parallelism for high-speed designs\n- Synchronous vs. asynchronous communication protocols (SPI\, SCI\, UART\, LVDS\, I2C\, PCIe\, USB\, Ethe rnet\, etc.)\n- Compare hardware/software/firmware implementations of ML: throughput speeds\, resource utilization\, and latency\n- Methods used to achieve ultra-high sampling rates (>> system clock\, GS/s range)\n- Utiliz ing advanced IP cores and IO buffers for high-speed interfaces and data st orage\n\n- Advanced FPGA Techniques for High-speed Systems\n- Clock domain crossing verification and synchronization techniques\n- Resource utilizat ion\, critical path identification\, and optimization strategies\n- Timing constraints\, static and dynamic timing analysis\n- Signal integrity anal ysis\n\n- High-Speed Design Verification and Testing\n- Simulation-based v erification techniques\, advanced debugging\, and waveform analysis\n- Pos t-layout verification and back-annotation\n- Test and validation strategie s for high-speed designs\n- Utilizing debug cores for real-time logic anal ysis\n\n- Machine Learning on FPGAs\n- Algorithm validation and verificati on in software\n- Compare capabilities and implementation strategies of ML on FPGAs\, SoCs\, and SoMs\n- Optimization strategies for efficient ML im plementation in hardware (e.g.\, convolution)\n\n- Digital Systems in Indu stry\n- Techniques and best practices for scalable\, reusable\, reliable\, and robust FPGA design\n- Board-level considerations for high-speed signa ls: PCB layout guidelines\, power distribution and decoupling\, transmissi on line theory and termination techniques\n- Emerging trends for FPGA-base d digital signal processing (DSP) applications\n\n________________________ ________________________________________________________________________\n \nSpeaker(s): Kendall Farnham\, PhD\, \n\nRoom: 2C130\, Bldg: Center\, MIT RE Corporation and On-Line\, 202 Burlington Road\, Bedford \, Massachusett s\, United States\, Virtual: https://events.vtools.ieee.org/m/371709 LOCATION:Room: 2C130\, Bldg: Center\, MITRE Corporation and On-Line\, 202 B urlington Road\, Bedford \, Massachusetts\, United States\, Virtual: https ://events.vtools.ieee.org/m/371709 ORGANIZER:k.safina@ieee.org SEQUENCE:24 SUMMARY:Advanced Digital Design: Implementing Deep Machine Learning on FPGA URL;VALUE=URI:https://events.vtools.ieee.org/m/371709 X-ALT-DESC:Description: <br /><p><strong>This course has been canceled! </s trong></p>\n<p>Course:&nbsp\; 4 weeks\, 1 class weekly\,&nbsp\; evening.&n bsp\; &nbsp\;Rates are listed below.&nbsp\; &nbsp\;September 16\, 23\, 30 and October 7\, 2024.We can offer Continuing Education Units (CEU) and Pro fessional Development Hours (PDH)\, if requested.&nbsp\; A small fee may a pply for the credits.</p>\n<p><strong>Course Overview: </strong></p>\n<p>F ield-programmable gate arrays (FPGAs) are versatile integrated circuits th at offer a flexible and reconfigurable hardware platform for implementing custom digital circuits\, particularly in applications requiring specializ ed architectures. Unlike application-specific integrated circuits (ASICs)\ , FPGAs can be programmed and reprogrammed after manufacturing using hardw are description languages (HDLs)\, enabling rapid prototyping and iterativ e design processes. FPGAs can be found in telecommunications\, signal proc essing\, aerospace\, and other scenarios demanding high-performance comput ing\, parallel processing\, low-latency data processing\, and real-time op erations. The newest trends include integrating FPGAs with systems on chip (SoCs) for implementing low-latency machine learning (ML) and artificial intelligence.</p>\n<p>This Advanced Digital Design course is an intensive program designed to build upon foundational concepts in digital logic desi gn and equip students with the skills needed to implement robust high-spee d ML algorithms on an FPGA. Through a combination of theoretical lectures\ , hands-on exercises\, and practical projects\, students will explore adva nced FPGA topics encompassing architectural considerations\, signal integr ity\, timing analysis\, and optimization techniques to achieve reliable an d efficient high-speed designs. Additionally\, this course will encourage students to explore current research papers and real-world industry applic ations to foster a deeper appreciation for advancements in state-of-the-ar t FPGA design. &nbsp\;&nbsp\;</p>\n<p><strong>Target audience:</strong> St udents and professionals with a base knowledge of FPGA design looking to a dvance hardware design skills for developing complex customized circuits f or efficient implementation of ML.</p>\n<p><strong>Benefits of attending:< /strong></p>\n<ul>\n<li>Valuable professional development creating skills that lead to job offers</li>\n<li>Reinforce and expand knowledge of VHDL a nd FPGA-specific design methodology.</li>\n<li>Develop skills for implemen ting high-speed\, robust\, reliable circuits on FPGAs.</li>\n<li>Gain unde rstanding of real-world industry applications of FPGAs and SoCs.</li>\n</u l>\n<p><strong>Course Objectives: </strong>By the end of this course\, stu dents will possess the expertise needed to tackle complex high-speed hardw are design challenges using FPGAs. They will be well-prepared to contribut e to cutting-edge research\, industry projects\, and advancements in areas such as telecommunications\, data centers\, embedded systems\, and high-p erformance computing.</p>\n<p><strong>Prerequisites:</strong></p>\n<ul>\n< li>Understanding of digital logic design principles and methodology (e.g.\ , Boolean algebra\, finite state machines\, data path elements)</li>\n<li> Familiarity with VHDL programming (or Verilog)</li>\n<li>Experience with F PGA development boards and tools (e.g.\, Vivado)</li>\n</ul>\n<p><strong>D etailed Course Outline: </strong></p>\n<ol>\n<li>Review of Digital Logic D esign and FPGA Programming\n<ul>\n<li>Boolean algebra\, combinational and sequential circuits\, finite state machines</li>\n<li>FPGA\, SoC\, and SoM architectures and toolchains</li>\n<li>VHDL programming techniques and de sign methodology</li>\n<li>Writing effective testbenches\, RTL simulation in Vivado</li>\n<li>Introduction to ML algorithms and FPGA-specific optimi zation strategies</li>\n</ul>\n</li>\n<li>High-throughput Communication on FPGAs\n<ul>\n<li>Pipelining and parallelism for high-speed designs</li>\n <li>Synchronous vs. asynchronous communication protocols (SPI\, SCI\, UART \, LVDS\, I2C\, PCIe\, USB\, Ethernet\, etc.)</li>\n<li>Compare hardware/s oftware/firmware implementations of ML: throughput speeds\, resource utili zation\, and latency</li>\n<li>Methods used to achieve ultra-high sampling rates (&gt\;&gt\; system clock\, GS/s range)</li>\n<li>Utilizing advanced IP cores and IO buffers for high-speed interfaces and data storage</li>\n </ul>\n</li>\n<li>Advanced FPGA Techniques for High-speed Systems\n<ul>\n< li>Clock domain crossing verification and synchronization techniques</li>\ n<li>Resource utilization\, critical path identification\, and optimizatio n strategies</li>\n<li>Timing constraints\, static and dynamic timing anal ysis</li>\n<li>Signal integrity analysis</li>\n</ul>\n</li>\n<li>High-Spee d Design Verification and Testing\n<ul>\n<li>Simulation-based verification techniques\, advanced debugging\, and waveform analysis</li>\n<li>Post-la yout verification and back-annotation</li>\n<li>Test and validation strate gies for high-speed designs</li>\n<li>Utilizing debug cores for real-time logic analysis</li>\n</ul>\n</li>\n<li>Machine Learning on FPGAs\n<ul>\n<l i>Algorithm validation and verification in software</li>\n<li>Compare capa bilities and implementation strategies of ML on FPGAs\, SoCs\, and SoMs</l i>\n<li>Optimization strategies for efficient ML implementation in hardwar e (e.g.\, convolution)</li>\n</ul>\n</li>\n<li>Digital Systems in Industry \n<ul>\n<li>Techniques and best practices for scalable\, reusable\, reliab le\, and robust FPGA design</li>\n<li>Board-level considerations for high- speed signals: PCB layout guidelines\, power distribution and decoupling\, transmission line theory and termination techniques</li>\n<li>Emerging tr ends for FPGA-based digital signal processing (DSP) applications</li>\n</u l>\n</li>\n</ol>\n<p>_____________________________________________________ ___________________________________________</p>\n<p>&nbsp\;</p> END:VEVENT END:VCALENDAR