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DTSTART:20230312T030000
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DTSTART:20231105T010000
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DTSTAMP:20231019T020003Z
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DTSTART;TZID=America/Los_Angeles:20230906T100000
DTEND;TZID=America/Los_Angeles:20230906T110000
DESCRIPTION:Technical Seminat by Dr. Kemal Aygün (Intel Fellow\, IEEE Fell
 ow) with the following abstract:\n\nRecently\, applications such as artifi
 cial intelligence has been evolving very rapidly and bringing with it a mo
 re stringent set of requirements for system performance. One area where th
 e performance demand has been scaling very aggressively is that for interc
 onnecting different components in an electronic system using high speed si
 gnaling. To address this demand\, the pace of innovation in electronic pac
 kaging has also increased greatly in recent years\, bringing with it a new
  set of challenges for electrical design\, analysis\, and validation. This
  presentation will review some of the recent developments in electronic pa
 ckaging technologies and corresponding electrical analysis and validation 
 methodologies and metrologies to address some of these challenges. It will
  also summarize some of the recent advancements on standardization of on-p
 ackage high speed signaling interconnects with a focus on Universal Chiple
 t Interconnect Express (UCIe).\n\nSpeaker(s): Kemal Aygün\n\nVancouver\, 
 British Columbia\, Canada\, Virtual: https://events.vtools.ieee.org/m/3723
 42
LOCATION:Vancouver\, British Columbia\, Canada\, Virtual: https://events.vt
 ools.ieee.org/m/372342
ORGANIZER:
SEQUENCE:7
SUMMARY:Advancements in Package High-Speed Signalling and Standardization
URL;VALUE=URI:https://events.vtools.ieee.org/m/372342
X-ALT-DESC:Description: <br /><p>Technical Seminat by Dr. Kemal Ayg&uuml\;n
  (Intel Fellow\, IEEE Fellow) with the following abstract:</p>\n<p>Recentl
 y\, applications such as artificial intelligence has been evolving very ra
 pidly and bringing with it a more stringent set of requirements for system
  performance. One area where the performance demand has been scaling very 
 aggressively is that for interconnecting different components in an electr
 onic system using high speed signaling. To address this demand\, the pace 
 of innovation in electronic packaging has also increased greatly in recent
  years\, bringing with it a new set of challenges for electrical design\, 
 analysis\, and validation. This presentation will review some of the recen
 t developments in electronic packaging technologies and corresponding elec
 trical analysis and validation methodologies and metrologies to address so
 me of these challenges. It will also summarize some of the recent advancem
 ents on standardization of on-package high speed signaling interconnects w
 ith a focus on Universal Chiplet Interconnect Express (UCIe).</p>
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