BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20230312T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20231105T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20230922T173417Z UID:46602866-E320-4F94-A132-3B0D509815A7 DTSTART;TZID=America/Los_Angeles:20230915T173000 DTEND;TZID=America/Los_Angeles:20230915T193000 DESCRIPTION:Abstract:\n\nSignal Integrity is critical to the design of high -performing and reliable semiconductor products.\n\nAs the data rates incr ease rapidly in high-speed systems\, the signal integrity has become a key factor to meet the bandwidth growth intensified by various applications.\ n\nIn this presentation\, we will start with the review of the basics of s ignal integrity and examine the key electrical characteristics of intercon nects: signal loss\, signal crosstalk\, return loss\, mode conversion and other important factors necessary to meet the performance requirements of the latest electronic systems.\n\nThen\, the interactions between the sign aling\, clocking\, equalization and modulation of the various interfaces w ill be discussed to explain how those interactions determine the achievabl e data rates. Finally\, the presentation will be concluded by reviewing va rious signal integrity modeling and simulation techniques.\n\nBiography:\n \nDr. Wendem T. Beyene was born in Addis Ababa\, Ethiopia. He received the B.S. and M.S. degrees in electrical engineering from Columbia University\ , New York\, NY\, USA\, in 1988 and 1991\, respectively\, and the Ph.D. de gree in electrical and computer engineering from the University of Illinoi s at Urbana-Champaign\, USA\, in 1997. In the past\, he was employed by IB M\, Hewlett-Packard\, and Agilent Technologies. In 2000\, he joined Rambus Inc.\, Los Altos\, CA\, USA\, and was responsible for signal integrity of multi-gigabit parallel and serial interfaces. During 2017-2020 he worked at Intel and was responsible for signal and power integrity analysis of hi gh-performance FPGA including fabric and high-speed I/O subsystems as well as I/O modeling. In 2020 he joined Facebook (Meta Platforms) as an Analog & Mixed-Signal Architect in Meta Reality Lab.\n\nDr. Beyene has authored numerous refereed IEEE publications in various disciplines including packa ge and interconnect modeling\, interface design and analysis as well as ap plication of machine learning and optimization techniques to signal and po wer integrity of complex systems. He is currently a Senior Area Editor - E lectrical Performance of Integrated Systems of IEEE Trans. On CPMT and is a Senior Member of IEEE. He also has served as distinguished lecturer for IEEE EMCS (Electromagnetic Compatibility Society) and IEEE EPS (Electrical Packaging Society).\n\nCo-sponsored by: CH06184\n\nSpeaker(s): \, Wendem Beyene\n\nBldg: 1st Floor\, Cupertino Public Library\, Cupertino\, Califor nia\, United States\, 95014 LOCATION:Bldg: 1st Floor\, Cupertino Public Library\, Cupertino\, Californi a\, United States\, 95014 ORGANIZER:nandish@ieee.org SEQUENCE:21 SUMMARY:An overview of Signal Integrity URL;VALUE=URI:https://events.vtools.ieee.org/m/372621 X-ALT-DESC:Description: <br /><p>Abstract:</p>\n<p>Signal Integrity is crit ical to the design of high-performing and reliable semiconductor products. </p>\n<p>As the data rates increase rapidly in high-speed systems\, the si gnal integrity has become a key factor to meet the bandwidth growth intens ified by various applications.&nbsp\;&nbsp\;</p>\n<p>In this presentation\ , we will start with the review of the basics of signal integrity and exam ine the key electrical characteristics of interconnects: signal loss\, sig nal crosstalk\, return loss\, mode conversion and other important factors necessary to meet the performance requirements of the latest electronic sy stems.</p>\n<p>Then\, the interactions between the signaling\, clocking\, equalization and modulation of the various interfaces will be discussed to explain how those interactions determine the achievable data rates. Final ly\, the presentation will be concluded by reviewing various signal integr ity modeling and simulation techniques.</p>\n<p><span class="sublabel">Bio graphy:</span></p>\n<p>Dr. Wendem T. Beyene was born in Addis Ababa\, Ethi opia. He received the B.S. and M.S. degrees in electrical engineering from Columbia University\, New York\, NY\, USA\, in 1988 and 1991\, respective ly\, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign\, USA\, in 1997. In the past\, he was employed by IBM\, Hewlett-Packard\, and Agilent Technologies. In 20 00\, he joined Rambus Inc.\, Los Altos\, CA\, USA\, and was responsible fo r signal integrity of multi-gigabit parallel and serial interfaces. During 2017-2020 he worked at Intel and was responsible for signal and power int egrity analysis of high-performance FPGA including fabric and high-speed I /O subsystems as well as I/O modeling. In 2020 he joined Facebook (Meta Pl atforms) as an Analog &amp\; Mixed-Signal Architect in Meta Reality Lab.</ p>\n<p>Dr. Beyene has authored numerous refereed IEEE publications in vari ous disciplines including package and interconnect modeling\, interface de sign and analysis as well as application of machine learning and optimizat ion techniques to signal and power integrity of complex systems. He is cur rently a Senior Area Editor - Electrical Performance of Integrated Systems of IEEE Trans. On CPMT and is a Senior Member of IEEE. He also has served as distinguished lecturer for IEEE EMCS (Electromagnetic Compatibility So ciety) and IEEE EPS (Electrical Packaging Society).</p> END:VEVENT END:VCALENDAR