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DESCRIPTION:Neural network (NN) models are rapidly increasing in size and c
 omplexity\, surpassing the pace of NN chip upgrades. The development of mo
 nolithic chips to match these evolving models is both expensive and challe
 nging.\n\nAlternatively\, modular chiplets can be designed and reused to c
 reate multi-chip packages (MCPs) capable of addressing diverse NN models a
 nd tasks. The future success of chiplet technology hinges on advancements 
 in chiplets that offer high utilization and flexibility\, efficient high-b
 andwidth die-to-die interfaces\, and high-density packaging.\n\nIn this pr
 esentation\, I will introduce two MCPs resulting from our collaboration wi
 th Intel and the Institute of Microelectronics in Singapore. The first MCP
 \, NetFlex\, integrates four NN chiplets using high- density fan-out wafer
  level packaging (HD-FOWLP). NetFlex’s flexible chiplet design and light
 weight die-to-die interface enable scalability for larger configurations.\
 n\nThe second MCP\, Arvon\, utilizes Embedded Multi-die Interconnect Bridg
 e (EMIB) to integrate an FPGA chiplet and two DSP chiplets. Arvon is a\npr
 ogrammable MCP that supports various workloads\, including NN and communic
 ation signal processing. Its flexibility allows for scalability to\naccomm
 odate evolving workloads over time.\n\nSpeaker(s): Zhengya Zhang \, \n\nVi
 rtual: https://events.vtools.ieee.org/m/372664
LOCATION:Virtual: https://events.vtools.ieee.org/m/372664
ORGANIZER:stefano.pietri@nxp.com
SEQUENCE:30
SUMMARY:Feed Your Mind - Chiplet approaches to scale up and scale out machi
 ne learning computation
URL;VALUE=URI:https://events.vtools.ieee.org/m/372664
X-ALT-DESC:Description: <br /><p>Neural network (NN) models are rapidly inc
 reasing in size and complexity\, surpassing the pace of NN chip upgrades. 
 The development of monolithic chips to match these evolving models is both
  expensive and challenging.</p>\n<p>Alternatively\, modular chiplets can b
 e designed and reused to create multi-chip packages (MCPs) capable of addr
 essing diverse NN models and tasks. The future success of chiplet technolo
 gy hinges on advancements in chiplets that offer high utilization and flex
 ibility\, efficient high-bandwidth die-to-die interfaces\, and high-densit
 y packaging.</p>\n<p>In this presentation\, I will introduce two MCPs resu
 lting from our collaboration with Intel and the Institute of Microelectron
 ics in&nbsp\;Singapore. The first MCP\, NetFlex\, integrates four NN chipl
 ets using high- density fan-out wafer level packaging (HD-FOWLP). NetFlex&
 rsquo\;s flexible&nbsp\;chiplet design and lightweight die-to-die interfac
 e enable scalability for larger configurations.</p>\n<p>The second MCP\, A
 rvon\, utilizes Embedded Multi-die Interconnect Bridge (EMIB) to integrate
  an FPGA chiplet and two DSP chiplets. Arvon is a<br />programmable MCP th
 at supports various workloads\, including NN and communication signal proc
 essing. Its flexibility allows for scalability to<br />accommodate evolvin
 g workloads over time.&nbsp\;</p>
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