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DTSTART:20231105T010000
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DTSTAMP:20231013T133230Z
UID:4F9894DF-B0DC-4F1C-995F-335A42498749
DTSTART;TZID=America/New_York:20231005T110000
DTEND;TZID=America/New_York:20231005T120000
DESCRIPTION:Noise-Shaping (NS) SAR ADCs become popular recently thanks to t
 heir low-power and high-resolution features. This presentation first summa
 rizes and benchmarks different discrete-time (DT) NS-SAR implementations i
 n literature. An open-loop duty-cycled residue amplifier is selected as a 
 power-efficient solution to realize high residue gain. Then\, a digital-pr
 edicted mismatch error shaping technique is introduced to improve the DAC 
 linearity. The proposed DT NS-SAR ADC achieves 80 dB SNDR\, 98 dB SFDR in 
 a 31.25 kHz bandwidth while consuming 7.3 μW. Next\, the NS-SAR architect
 ure is extended from DT operation to continuous-time (CT) operation. The A
 DC sampling switch is removed and the loop filter is duty cycled to realiz
 e the CT NS-SAR operation. Compared to DT designs\, the CT NS-SAR ADC is e
 asy to drive and has inherent anti-aliasing function. As a proof of concep
 t\, the proposed CT NS-SAR ADC achieves 77 dB SNDR\, 86 dB SFDR a 62.5 kHz
  bandwidth with a power consumption of 13.5 μW.\n\nSpeaker(s): Prof. Piet
 er Harpe\n\nAgenda: \nThis talk will be held virtually. The talk will star
 t with speaker introduction followd by a technical session. Afterwards\, a
  QA session.\n\nVirtual: https://events.vtools.ieee.org/m/373982
LOCATION:Virtual: https://events.vtools.ieee.org/m/373982
ORGANIZER:wagih.ismail@iee.org
SEQUENCE:29
SUMMARY:Noise-Shaping SAR ADCs: From Discrete Time to Continuous Time
URL;VALUE=URI:https://events.vtools.ieee.org/m/373982
X-ALT-DESC:Description: <br /><p>Noise-Shaping (NS) SAR ADCs become popular
  recently thanks to their low-power and high-resolution features. This pre
 sentation first summarizes and benchmarks different discrete-time (DT) NS-
 SAR implementations in literature. An open-loop duty-cycled residue amplif
 ier is selected as a power-efficient solution to realize high residue gain
 . Then\, a digital-predicted mismatch error shaping technique is introduce
 d to improve the DAC linearity. The proposed DT NS-SAR ADC achieves 80 dB 
 SNDR\, 98 dB SFDR in a 31.25 kHz bandwidth while consuming 7.3 &mu\;W. Nex
 t\, the NS-SAR architecture is extended from DT operation to continuous-ti
 me (CT) operation. The ADC sampling switch is removed and the loop filter 
 is duty cycled to realize the CT NS-SAR operation. Compared to DT designs\
 , the CT NS-SAR ADC is easy to drive and has inherent anti-aliasing functi
 on. As a proof of concept\, the proposed CT NS-SAR ADC achieves 77 dB SNDR
 \, 86 dB SFDR a 62.5 kHz bandwidth with a power consumption of 13.5 &mu\;W
 .</p><br /><br />Agenda: <br /><p>This talk will be held virtually. The ta
 lk will start with speaker introduction followd by a technical session. Af
 terwards\, a QA session.&nbsp\;</p>
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