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DTSTAMP:20250107T005503Z
UID:BEF79193-11DD-477D-A6F6-BCB1E631C830
DTSTART;TZID=America/Los_Angeles:20231024T100000
DTEND;TZID=America/Los_Angeles:20231024T110000
DESCRIPTION:Technical Seminar by Dr. Ramin Farjadrad with the following abs
 tract:\n\nFor the past 4 decades\, industry has supported 2x conpute perfo
 rmance increase every 2 years\, a trend supported by Moore’s Law. Howeve
 r\, not only has Moore’s law come to an end\, but also the exponential d
 emand for more AI/HPC had driven the performance demand close to 10x/year.
  This recent trend has resulted in the chips growing significantly in size
 \, to include more compute cores\, exceeding maximum chip manufacturing di
 mensions.\nThe chiplet system-in-package (SiP) enables implementing very l
 arge processor chips by connecting several smaller chiplets. These chiplet
 s must be connected at very high bandwidth and low power\, to perform like
  a single chip. Advanced packaging technologies like silicon interposers a
 re developed to connect chiplets at the target bandwidths/powers. However\
 , advanced packaging solutions\, besides being super expensive\, come with
  many limitations. A major limitation is their supply chain. Currently\, T
 SMC is the sole provider of large Silicon Interposers that are critical fo
 r AI/HPC chips. Even without any geopolitical risk that may limit TSMC’s
  suppl\, TSMC cannot deliver the worldwide interposer demand in near futur
 e.\nThis presentation introduces novel chiplet connectivity technologies t
 hat enables creating high-end AI/HPC chips without the need for large inte
 rposers.\n\nSpeaker(s): \, Ramin Farjadrad\n\nVancouver\, British Columbia
 \, Canada\, Virtual: https://events.vtools.ieee.org/m/379704
LOCATION:Vancouver\, British Columbia\, Canada\, Virtual: https://events.vt
 ools.ieee.org/m/379704
ORGANIZER:
SEQUENCE:15
SUMMARY:Novel Chiplet Connectivity Technologies For Enabling High-end AI/HP
 C
URL;VALUE=URI:https://events.vtools.ieee.org/m/379704
X-ALT-DESC:Description: <br /><p>Technical Seminar by Dr. Ramin Farjadrad w
 ith the following abstract:</p>\n<p>For the past 4 decades\, industry has 
 supported 2x conpute performance increase every 2 years\, a trend supporte
 d by Moore&rsquo\;s Law. However\, not only has Moore&rsquo\;s law come to
  an end\, but also the exponential demand for more AI/HPC had driven the p
 erformance demand close to 10x/year. This recent trend has resulted in the
  chips growing significantly in size\, to include more compute cores\, exc
 eeding maximum chip manufacturing dimensions.<span class="apple-converted-
 space">&nbsp\;</span><br />The chiplet system-in-package (SiP) enables imp
 lementing very large processor chips by connecting several smaller chiplet
 s. These chiplets must be connected at very high bandwidth and low power\,
  to perform like a single chip. Advanced packaging technologies like silic
 on interposers are developed to connect chiplets at the target bandwidths/
 powers. However\, advanced packaging solutions\, besides being super expen
 sive\, come with many limitations. A major limitation is their supply chai
 n. Currently\, TSMC is the sole provider of large Silicon Interposers that
  are critical for AI/HPC chips. Even without any geopolitical risk that ma
 y limit TSMC&rsquo\;s suppl\, TSMC cannot deliver the worldwide interposer
  demand in near future.<span class="apple-converted-space">&nbsp\;</span><
 br />This presentation introduces novel chiplet connectivity technologies 
 that enables creating high-end AI/HPC chips without the need for large int
 erposers.</p>
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