BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Denver BEGIN:DAYLIGHT DTSTART:20240310T030000 TZOFFSETFROM:-0700 TZOFFSETTO:-0600 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:MDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20231105T010000 TZOFFSETFROM:-0600 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:MST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20231117T151128Z UID:7B5F6888-3A79-4735-A16C-7DADBF475BD1 DTSTART;TZID=America/Denver:20231116T183000 DTEND;TZID=America/Denver:20231116T203000 DESCRIPTION:Abstract:\n\nFor decades\, Moore’s Law has delivered the abil ity to integrate an exponentially increasing number of devices in the same silicon area at a roughly constant cost. This has enabled tremendous leve ls of integration\, where the capabilities of computer systems that previo usly occupied entire rooms can now fit on a single integrated circuit.\n\n In recent times\, the steady drum beat of Moore’s Law has started to slo w down. Whereas device density historically doubled every 18-24 months\, t he rate of recent silicon process advancements has declined. While improve ments in device scaling continue\, albeit at a reduced pace\, the industry is simultaneously observing increases in manufacturing costs. In response \, the industry is now seeing a trend toward reversing direction on the tr aditional march toward more integration. Instead\, multiple industry and a cademic groups are advocating that systems on chips (SoCs) be “disintegr ated” into multiple smaller “chiplets.” This talk details the techno logy challenges that motivated AMD to use chiplets\, the technical solutio ns we developed for our products\, and how we expanded the use of chiplets from individual processors to multiple product families. From this founda tion\, we will look toward the future of chiplet and 3D architectures that will require multi-disciplinary innovation across package technology\, si licon design\, accelerators\, and the software to exploit them.\n\nSpeaker (s): Samuel\, \n\nBldg: Coy Barn Conference Center\, 1075 Woodward Way\, W oodward Corporate Campus\, Fort Collins\, Colorado\, United States\, 80524 \, Virtual: https://events.vtools.ieee.org/m/380847 LOCATION:Bldg: Coy Barn Conference Center\, 1075 Woodward Way\, Woodward Co rporate Campus\, Fort Collins\, Colorado\, United States\, 80524\, Virtual : https://events.vtools.ieee.org/m/380847 ORGANIZER:mag10co@hotmail.com SEQUENCE:17 SUMMARY:“How and Why 2.5D and 3D Integration is Revolutionizing Silicon D esign” URL;VALUE=URI:https://events.vtools.ieee.org/m/380847 X-ALT-DESC:Description: <br /><p>Abstract:</p>\n<p>For decades\, Moore&rsqu o\;s Law has delivered the ability to integrate an exponentially increasin g number of devices in the same silicon area at a roughly constant cost.&n bsp\; This has enabled tremendous levels of integration\, where the capabi lities of computer systems that previously occupied entire rooms can now f it on a single integrated circuit.</p>\n<p>In recent times\, the steady dr um beat of Moore&rsquo\;s Law has started to slow down.&nbsp\; Whereas dev ice density historically doubled every 18-24 months\, the rate of recent s ilicon process advancements has declined.&nbsp\; While improvements in dev ice scaling continue\, albeit at a reduced pace\, the industry is simultan eously observing increases in manufacturing costs.&nbsp\; In response\, th e industry is now seeing a trend toward reversing direction on the traditi onal march toward more integration.&nbsp\; Instead\, multiple industry and academic groups are advocating that systems on chips (SoCs) be &ldquo\;di sintegrated&rdquo\; into multiple smaller &ldquo\;chiplets.&rdquo\;&nbsp\; This talk details the technology challenges that motivated AMD to use chi plets\, the technical solutions we developed for our products\, and how we expanded the use of chiplets from individual processors to multiple produ ct families.&nbsp\; From this foundation\, we will look toward the future of chiplet and 3D architectures that will require multi-disciplinary innov ation across package technology\, silicon design\, accelerators\, and the software to exploit them.</p>\n<p>&nbsp\;</p> END:VEVENT END:VCALENDAR