BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Jerusalem BEGIN:DAYLIGHT DTSTART:20240329T030000 TZOFFSETFROM:+0200 TZOFFSETTO:+0300 RRULE:FREQ=YEARLY;BYDAY=-1FR;BYMONTH=3 TZNAME:IDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20231029T010000 TZOFFSETFROM:+0300 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:IST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20240101T125156Z UID:10D4AC56-50A8-462E-9D7D-928E0F49E66D DTSTART;TZID=Asia/Jerusalem:20231207T160000 DTEND;TZID=Asia/Jerusalem:20231207T173000 DESCRIPTION:Abstract\n\nNeural network (NN) models are rapidly increasing i n size and complexity\, surpassing the pace of NN chip upgrades. The devel opment of monolithic chips to match these evolving models is both expensiv e and challenging. Alternatively\, modular chiplets can be designed and re used to create multi-chip packages (MCPs) capable of addressing diverse NN models and tasks. The future success of chiplet technology hinges on adva ncements in chiplets that offer high utilization and flexibility\, efficie nt high-bandwidth die-to-die interfaces\, and high-density packaging. In t his presentation\, I will introduce two MCPs resulting from our collaborat ion with Intel and the Institute of Microelectronics in Singapore. The fir st MCP\, NetFlex\, integrates four NN chiplets using high-density fan-out wafer level packaging (HD-FOWLP). NetFlex’s flexible chiplet design and lightweight die-to-die interface enable scalability for larger configurati ons. The second MCP\, Arvon\, utilizes Embedded Multi-die Interconnect Bri dge (EMIB) to integrate an FPGA chiplet and two DSP chiplets. Arvon is a p rogrammable MCP that supports various workloads\, including NN and communi cation signal processing. Its flexibility allows for scalability to accomm odate evolving workloads over time.\n\nBio\n\nZhengya Zhang received the B .A.Sc. degree from the University of Waterloo in 2003\, and the M.S. and P h.D. degrees from UC Berkeley in 2005 and 2009\, respectively. Since 2009\ , he has been with the Department of Electrical Engineering and Computer S cience at the University of Michigan\, Ann Arbor\, where he is currently a full professor. His research primarily focuses on low-power and high-perf ormance VLSI circuits and systems\, with applications in computing\, commu nications\, and signal processing. Dr. Zhang was a recipient of the NSF CA REER Award\, the Intel Early Career Faculty Award\, the University of Mich igan Neil Van Eenam Memorial Award\, and the David J. Sakrison Memorial Pr ize from UC Berkeley. He serves as an IEEE Solid-State Circuits Society Di stinguished Lecturer.\n\nVirtual: https://events.vtools.ieee.org/m/387202 LOCATION:Virtual: https://events.vtools.ieee.org/m/387202 ORGANIZER:shahar@ee.technion.ac.il SEQUENCE:8 SUMMARY:Chiplet approaches to scale up and scale out machine learning compu tation\, Prof. Zhengya Zhang\, University of Michigan\, Ann Arbor URL;VALUE=URI:https://events.vtools.ieee.org/m/387202 X-ALT-DESC:Description: <br /><p><strong>Abstract</strong></p>\n<p>Neural n etwork (NN) models are rapidly increasing in size and complexity\, surpass ing the pace of NN chip upgrades. The development of monolithic chips to m atch these evolving models is both expensive and challenging. Alternativel y\, modular chiplets can be designed and reused to create multi-chip packa ges (MCPs) capable of addressing diverse NN models and tasks. The future s uccess of chiplet technology hinges on advancements in chiplets that offer high utilization and flexibility\, efficient high-bandwidth die-to-die in terfaces\, and high-density packaging. In this presentation\, I will intro duce two MCPs resulting from our collaboration with Intel and the Institut e of Microelectronics in Singapore. The first MCP\, NetFlex\, integrates f our NN chiplets using high-density fan-out wafer level packaging (HD-FOWLP ). NetFlex&rsquo\;s flexible chiplet design and lightweight die-to-die int erface enable scalability for larger configurations. The second MCP\, Arvo n\, utilizes Embedded Multi-die Interconnect Bridge (EMIB) to integrate an FPGA chiplet and two DSP chiplets. Arvon is a programmable MCP that suppo rts various workloads\, including NN and communication signal processing. Its flexibility allows for scalability to accommodate evolving workloads o ver time.</p>\n<p><strong>Bio</strong></p>\n<p>Zhengya Zhang received the B.A.Sc. degree from the University of Waterloo in 2003\, and the M.S. and Ph.D. degrees from UC Berkeley in 2005 and 2009\, respectively. Since 2009 \, he has been with the Department of Electrical Engineering and Computer Science at the University of Michigan\, Ann Arbor\, where he is currently a full professor. His research primarily focuses on low-power and high-per formance VLSI circuits and systems\, with applications in computing\, comm unications\, and signal processing. Dr. Zhang was a recipient of the NSF C AREER Award\, the Intel Early Career Faculty Award\, the University of Mic higan Neil Van Eenam Memorial Award\, and the David J. Sakrison Memorial P rize from UC Berkeley. He serves as an IEEE Solid-State Circuits Society D istinguished Lecturer.</p> END:VEVENT END:VCALENDAR