BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Europe/Warsaw
BEGIN:DAYLIGHT
DTSTART:20240331T030000
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3
TZNAME:CEST
END:DAYLIGHT
BEGIN:STANDARD
DTSTART:20231029T020000
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10
TZNAME:CET
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20231220T155739Z
UID:44AFF89F-ADC7-4A8E-85EC-E3D8417801FE
DTSTART;TZID=Europe/Warsaw:20231214T163000
DTEND;TZID=Europe/Warsaw:20231214T183000
DESCRIPTION:DAC/ADC Architectures\n\nThis tutorial is a continuation of lec
 tures given this year as a "Introduction to System and Circuit Design of A
 nalog to Digital Converters" and provides analysis and circuit design of A
 nalog to Digital Converters with special emphasis on its drawbacks and lim
 its. In the given lecture typical and well-known architectures will be pro
 vided and analyzed in detail.\n\nRoom: 224\, Bldg: C2\, AGH University\, A
 v. Mickiewicza 30\, Krakow\, Malopolskie\, Poland\, Virtual: https://event
 s.vtools.ieee.org/m/390538
LOCATION:Room: 224\, Bldg: C2\, AGH University\, Av. Mickiewicza 30\, Krako
 w\, Malopolskie\, Poland\, Virtual: https://events.vtools.ieee.org/m/39053
 8
ORGANIZER:krzysztof.kasinski@siliconcr.com
SEQUENCE:8
SUMMARY:Seminar: DAC/ADC Architectures (Prof. B. Staszewski\, UCD Dublin)
URL;VALUE=URI:https://events.vtools.ieee.org/m/390538
X-ALT-DESC:Description: <br /><p><strong>DAC/ADC Architectures</strong></p>
 \n<p>This tutorial is a continuation of lectures given this year as a "Int
 roduction to System and Circuit Design of Analog to Digital Converters" an
 d provides analysis and circuit design of Analog to Digital Converters wit
 h special emphasis on its drawbacks and limits. In the given lecture typic
 al and well-known architectures will be provided and analyzed in detail.</
 p>
END:VEVENT
END:VCALENDAR