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DTSTART:20240310T030000
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DTSTART:20231105T010000
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DTSTAMP:20240130T225135Z
UID:36EDFA0F-9FCC-4731-8172-51EBDDC323B1
DTSTART;TZID=America/Los_Angeles:20240129T173000
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DESCRIPTION:5:30pm: food and drink\n\n6:15pm: presentation\n\nIn recent yea
 rs\, there has been a surge in the use of machine learning techniques acro
 ss diverse domains\, including hardware design. With the growing complexit
 y of modern hardware systems\, there arises a compelling demand for the de
 velopment of more efficient and effective design methodologies. Machine le
 arning can play a pivotal role and offer capabilities that were not possib
 le in conventional ways. In this talk\, recent progress in machine learnin
 g applications in hardware design\, with a specific focus on SI/PI\, will 
 be introduced. The case studies include: 1) PDN impedance prediction\, 2) 
 pre/post-layout decap optimization\, and 3) stack-up optimization for SI.\
 n\nSpeaker(s): \, Chulsoon Hwang\n\n1120 Fulton Pl\, Fremont\, California\
 , United States\, 94539
LOCATION:1120 Fulton Pl\, Fremont\, California\, United States\, 94539
ORGANIZER:Caroline.chan.us@ieee.org
SEQUENCE:11
SUMMARY:Machine learning applications in hardware design: SIPI perspective
URL;VALUE=URI:https://events.vtools.ieee.org/m/398519
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;p&gt;5:30pm: food and drink&lt;/p&gt;
 \n&lt;p&gt;6:15pm: presentation&lt;/p&gt;\n&lt;p&gt;In recent years\, there has been a surge
  in the use of machine learning techniques across diverse domains\, includ
 ing hardware design. With the growing complexity of modern hardware system
 s\, there arises a compelling demand for the development of more efficient
  and effective design methodologies. Machine learning can play a pivotal r
 ole and offer capabilities that were not possible in conventional ways. In
  this talk\, recent progress in machine learning applications in hardware 
 design\, with a specific focus on SI/PI\, will be introduced. The case stu
 dies include: 1) PDN impedance prediction\, 2) pre/post-layout decap optim
 ization\, and 3) stack-up optimization for SI.&lt;/p&gt;
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