BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Kuala_Lumpur BEGIN:DAYLIGHT DTSTART:20380119T111407 TZOFFSETFROM:+0800 TZOFFSETTO:+0800 RRULE:FREQ=YEARLY;BYDAY=3TU;BYMONTH=1 TZNAME:+08 END:DAYLIGHT BEGIN:STANDARD DTSTART:19820101T000000 TZOFFSETFROM:+0730 TZOFFSETTO:+0800 RRULE:FREQ=YEARLY;BYDAY=1FR;BYMONTH=1 TZNAME:+08 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20240104T062208Z UID:1B672286-CD38-4AD3-B91D-311F3636C123 DTSTART;TZID=Asia/Kuala_Lumpur:20230722T180000 DTEND;TZID=Asia/Kuala_Lumpur:20230722T210000 DESCRIPTION:In July of 2023\, University of Nottingham Malaysia (UNM) stude nt Chia Yu Hang from the department of Electrical and Electronic Engineeri ng (EEE) won the IEEE Electronic Packaging Society’s (EPS) Best Engineer ing Student Award (BESA) for his Final Year Project (FYP) entitled “SRAM -based In-Memory Computing”\, under the supervision of Prof T. Nandha. T he award was presented to him by Dr Eu Poh Leng from the IEEE EPS society at the annual Faculty of Science and Engineering (FOSE) Awards Ceremony he ld at the Bangi Convention Center\, July 22nd\, 2023.\n\nYu Hang’s FYP t ackles the problem of limited computer data throughput caused by the physi cal separation of the computing elements (the CPU) and the memory elements (the RAM) necessitating information exchange between them on a shared-bus . This is traditionally known as the Von Neumann architecture and the resu lting limited throughput over the shared bus is called the Von Neumann bot tleneck. In 1945\, a Hungarian-American computer scientist\, John Von Neum ann proposed the computer architectural model that currently bears his nam e and is still the main architecture used on computing systems in producti on today. Due to the Von Neumann bottleneck\, the maximum throughput at wh ich computers can process data is currently limited by the rate of the seq uential data exchange on the bus.\n\nIn-memory computing (IMC) also known as Processing in Memory (PIM) is an alternative computer architecture para digm in which the computing elements and the memory elements are combined together in a single chip rather than having them separated and communicat ing across the system bus. In his FYP\, Yu Hang explored the use of SRAM i n the application of an IMC application\, in particular his project object ives included designing and evaluating an SRAM cell at the circuit level\, designing an IMC architecture using the SRAM cross-bar design\, designing a multiplier using the newly proposed IMC architecture and comparing his design with the pre-existing designs.\n\nIn his project Yu Hang compared h is designs to a 10-transistor SRAM design from the literature and subseque ntly was able to improve the design to an 8-transistor SRAM resulting in a 20% improvement over the state-of-the art.\n\nBangi\, Selangor\, Malaysia LOCATION:Bangi\, Selangor\, Malaysia ORGANIZER:splim@indium.com SEQUENCE:20 SUMMARY:Besa Award for Nottingham University URL;VALUE=URI:https://events.vtools.ieee.org/m/398923 X-ALT-DESC:Description: <br /><p>In July of 2023\, University of Nottingham Malaysia (UNM) student Chia Yu Hang from the department of Electrical and Electronic Engineering (EEE) won the IEEE Electronic Packaging Society&rs quo\;s (EPS) Best Engineering Student Award (BESA) for his Final Year Proj ect (FYP) entitled &ldquo\;SRAM-based In-Memory Computing&rdquo\;\, under the supervision of Prof T. Nandha. The award was presented to him by Dr Eu Poh Leng from the IEEE EPS society at the annual Faculty of Science and E ngineering (FOSE) Awards Ceremony held at the Bangi Convention Center\, Ju ly 22nd\, 2023.</p>\n<p>Yu Hang&rsquo\;s FYP tackles the problem of limite d computer data throughput caused by the physical separation of the comput ing elements (the CPU) and the memory elements (the RAM) necessitating inf ormation exchange between them on a shared-bus. This is traditionally know n as the Von Neumann architecture and the resulting limited throughput ove r the shared bus is called the Von Neumann bottleneck. In 1945\, a Hungari an-American computer scientist\, John Von Neumann proposed the computer ar chitectural model that currently bears his name and is still the main arch itecture used on computing systems in production today. Due to the Von Neu mann bottleneck\, the maximum throughput at which computers can process da ta is currently limited by the rate of the sequential data exchange on the bus.</p>\n<p>In-memory computing (IMC) also known as Processing in Memory (PIM) is an alternative computer architecture paradigm in which the compu ting elements and the memory elements are combined together in a single ch ip rather than having them separated and communicating across the system b us. In his FYP\, Yu Hang explored the use of SRAM in the application of an IMC application\, in particular his project objectives included designing and evaluating an SRAM cell at the circuit level\, designing an IMC archi tecture using the SRAM cross-bar design\, designing a multiplier using the newly proposed IMC architecture and comparing his design with the pre-exi sting designs.</p>\n<p>In his project Yu Hang compared his designs to a 10 -transistor SRAM design from the literature and subsequently was able to i mprove the design to an 8-transistor SRAM resulting in a 20% improvement o ver the state-of-the art.</p> END:VEVENT END:VCALENDAR