BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20240310T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20241103T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20240328T231456Z UID:E95CB2AC-9229-4CC8-A63D-BB524746D7E8 DTSTART;TZID=America/New_York:20240326T183000 DTEND;TZID=America/New_York:20240326T194500 DESCRIPTION:Chiplet is a chip design method and heterogeneous integration i s a chip packaging method. Chiplet design and heterogeneous integration pa ckaging have generated lots of traction lately. For the next few years\, w e will see more implementations of a higher level of chiplet designs and h eterogeneous integration packaging\, whether it is for cost\, time-to-mark et\, performance\, form factor\, or power consumption.\n\nSpeaker(s): John H Lau\, \n\nAgenda: \n6:10 PM: Networking and Refreshments\n\n6:30 PM: An nouncements and Speaker Introduction\n\n6:35 PM: DL\n\n7:30 PM: Questions and Answers\n\n7:45 PM: Adjourn\n\n============\n\nIn this lecture\, the f ollowing topics will be covered.\n\nSystem-on-Chip (SoC)\n\nWhy Chiplet De sign?\n\nChiplet Design and Heterogeneous Integration Packaging – Chip P artition and Chip Split\n\nChip partition and Heterogeneous Integration\n\ nChip split and Heterogeneous Integration\n\nAdvantages and Disadvantages\ n\nLateral Communication between Chiplets (e.g.\, Bridges)\n\nBridge Embed ded in Build-up Package Substrate\n\nBridge Embedded in Fan-Out EMC with R DLs\n\nUCIe\n\nHybrid Bonding Bridge\n\nChiplet Design and Heterogeneous I ntegration Packaging - Multiple System and Heterogeneous Integration\n\nMu ltiple System and Heterogeneous Integration with Package Substrate (2D IC Integration)\n\nMultiple System and Heterogeneous Integration with Thin Fi lm layer on the Package Substrate (2.1D IC Integration)\n\nMultiple System and Heterogeneous Integration with TSV-less (Organic) Interposer (2.3D IC Integration)\n\nMultiple System and Heterogeneous Integration with Passiv e TSV-Interposer (2.5D IC Integration)\n\nMultiple System and Heterogeneou s Integration with Active TSV-Interposer (3D IC Integration)\n\nSummary\n\ nPotential R&D Topics in Chiplet Design and Heterogeneous Integration Pack aging\n\nTrends in Chiplet Design and Heterogeneous Integration Packaging\ n\nWho Should Attend?\n\nIf you (students\, engineers\, and managers) are involved with any aspect of the electronics industry\, you should attend t his course. It is equally suited for R&D professionals and scientists. The lectures are based on the publications by many distinguish authors and th e books by the lecturer.\n\nRoom: 201 Bluemont Room\, Bldg: Arlington Cent ral Library\, 1015 North Quincy Street\, Arlington\, Virginia\, United Sta tes\, 22201\, Virtual: https://events.vtools.ieee.org/m/408058 LOCATION:Room: 201 Bluemont Room\, Bldg: Arlington Central Library\, 1015 N orth Quincy Street\, Arlington\, Virginia\, United States\, 22201\, Virtua l: https://events.vtools.ieee.org/m/408058 ORGANIZER:tonyguoxy@gmail.com SEQUENCE:28 SUMMARY:Chiplet Design and Heterogeneous Integration Packaging URL;VALUE=URI:https://events.vtools.ieee.org/m/408058 X-ALT-DESC:Description: <br /><p>Chiplet is a chip design method and hetero geneous integration is a chip packaging method. Chiplet design and heterog eneous integration packaging have generated lots of traction lately. For t he next few years\, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging\, whether it is fo r cost\, time-to-market\, performance\, form factor\, or power consumption .&nbsp\;</p><br /><br />Agenda: <br /><p>6:10 PM: Networking and Refreshme nts</p>\n<p>6:30 PM: Announcements and Speaker Introduction</p>\n<p>6:35 P M: DL</p>\n<p>7:30 PM: Questions and Answers</p>\n<p>7:45 PM: Adjourn</p>\ n<p>============</p>\n<p>In this lecture\, the following topics will be co vered.</p>\n<p>System-on-Chip (SoC)</p>\n<p>Why Chiplet Design?</p>\n<p>Ch iplet Design and Heterogeneous Integration Packaging &ndash\; Chip Partiti on and Chip Split</p>\n<p>Chip partition and Heterogeneous Integration</p> \n<p>Chip split and Heterogeneous Integration</p>\n<p>Advantages and Disad vantages</p>\n<p>Lateral Communication between Chiplets (e.g.\, Bridges)</ p>\n<p>Bridge Embedded in Build-up Package Substrate</p>\n<p>Bridge Embedd ed in Fan-Out EMC with RDLs</p>\n<p>UCIe</p>\n<p>Hybrid Bonding Bridge</p> \n<p>Chiplet Design and Heterogeneous Integration Packaging - Multiple Sys tem and Heterogeneous Integration</p>\n<p>Multiple System and Heterogeneou s Integration with Package Substrate (2D IC Integration)</p>\n<p>Multiple System and Heterogeneous Integration with Thin Film layer on the Package S ubstrate (2.1D IC Integration)</p>\n<p>Multiple System and Heterogeneous I ntegration with TSV-less (Organic) Interposer (2.3D IC Integration)</p>\n< p>Multiple System and Heterogeneous Integration with Passive TSV-Interpose r (2.5D IC Integration)</p>\n<p>Multiple System and Heterogeneous Integrat ion with Active TSV-Interposer (3D IC Integration)</p>\n<p>Summary</p>\n<p >Potential R&amp\;D Topics in Chiplet Design and Heterogeneous Integration Packaging</p>\n<p>Trends in Chiplet Design and Heterogeneous Integration Packaging</p>\n<p>Who Should Attend?</p>\n<p>If you (students\, engineers\ , and managers) are involved with any aspect of the electronics industry\, you should attend this course. It is equally suited for R&amp\;D professi onals and scientists. The lectures are based on the publications by many d istinguish authors and the books by the lecturer.</p> END:VEVENT END:VCALENDAR