BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD DTSTART:19451014T230000 TZOFFSETFROM:+0630 TZOFFSETTO:+0530 TZNAME:IST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20240311T053528Z UID:C023EF4E-2AD0-417E-87B0-32CF2179BBFD DTSTART;TZID=Asia/Kolkata:20240307T160000 DTEND;TZID=Asia/Kolkata:20240307T170000 DESCRIPTION:Compact/SPICE models of circuit elements (passive\, active\, ME MS\, RF\, Microwave\, Photonics) are essential to enable advanced IC desig n using nanoscaled semiconductor technologies. Compact/SPICE models are al so a communication means between the semiconductor foundries and the IC de sign teams to share and exchange all engineering and design information. F OSS IC design collaboration is increasingly possible due to the rapid grow th of open access PDKs recently offered by SkyWater\, GF and IHP. To explo re all related interactions\, we are discussing selected FOSS CAD tools al ong the complete technology/design tool chain from nanascaled technology p rocesses\; thru the compact modeling\; to advanced IC transistor level des ign support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Comp act modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data e xchange formats. Application and use of these tools for advanced IC design (e.g. analog/RF\, Microwave\, Photonics applications) directly depends on the quality of the compact model implementations in these tools as well a s reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap\, Xyce\, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization.\n\nSpeaker(s): Dr. Wladek G rabinski\n\nAuditorium\, Dept. of ESE\, IISc Bangalore\, Bengaluru\, Karna taka\, India\, 560012\, Virtual: https://events.vtools.ieee.org/m/408375 LOCATION:Auditorium\, Dept. of ESE\, IISc Bangalore\, Bengaluru\, Karnataka \, India\, 560012\, Virtual: https://events.vtools.ieee.org/m/408375 ORGANIZER:mayank@iisc.ac.in; nimithap@iisc.ac.in SEQUENCE:17 SUMMARY:FOSS TCAD/EDA Tools SPICE and Verilog: A Modeling Flow Technology - Devices – Applications URL;VALUE=URI:https://events.vtools.ieee.org/m/408375 X-ALT-DESC:Description: <br /><p>Compact/SPICE models of circuit elements ( passive\, active\, MEMS\, RF\, Microwave\, Photonics) are essential to ena ble advanced IC design using nanoscaled semiconductor technologies. Compac t/SPICE models are also a communication means between the semiconductor fo undries and the IC design teams to share and exchange all engineering and design information. FOSS IC design collaboration is increasingly possible due to the rapid growth of open access PDKs recently offered by SkyWater\, GF and IHP. To explore all related interactions\, we are discussing selec ted FOSS CAD tools along the complete technology/design tool chain from na nascaled technology processes\; thru the compact modeling\; to advanced IC transistor level design support. New technology and device development wi ll be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics rel ated to its parameter extraction and standardization of the experimental a nd measurement data exchange formats. Application and use of these tools f or advanced IC design (e.g. analog/RF\, Microwave\, Photonics applications ) directly depends on the quality of the compact model implementations in these tools as well as reliability of extracted models and generated libra ries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gn ucap\, Xyce\, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization.</p> END:VEVENT END:VCALENDAR