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DTSTAMP:20240315T193438Z
UID:525FA013-623F-42E7-A022-436FE4F984DF
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DESCRIPTION:[]Chiplet is a chip design method and heterogeneous integration
  is a chip packaging method. Chiplet design and heterogeneous integration 
 packaging have been generated lots of tractions lately. For the next few y
 ears\, we will see more implementations of a higher level of chiplet desig
 ns and heterogeneous integration packaging\, whether it is for cost\, time
 -to-market\, performance\, form factor\, or power consumption. In this lec
 ture\, the following topics will be covered: (1) System-on-Chip (SoC)\; (2
 ) Why Chiplet Design\; (3) Chiplet Design and Heterogeneous Integration Pa
 ckaging (a) Chip Partition and Chip Split\, (b) Chip partition and Heterog
 eneous Integration\, (c) Chip split and Heterogeneous Integration\, and (d
 ) Advantages and Disadvantages\; (4) Lateral Communication between Chiplet
 s (e.g.\, Bridges) (a) Bridge Embedded in Build-up Package Substrate\, (b)
  Bridge Embedded in Fan-Out EMC with RDLs\, (c) UCIe\, and (d) Hybrid Bond
 ing Bridge\; (5) Chiplet Design and Heterogeneous Integration Packaging (a
 ) Multiple System and Heterogeneous Integration with Package Substrate (2D
  IC Integration)\, (b) Multiple System and Heterogeneous Integration with 
 Thin Film layer on the Package Substrate (2.1D IC Integration)\, (c) Multi
 ple System and Heterogeneous Integration with TSV-less (Organic) Interpose
 r (2.3D IC Integration)\, (d) Multiple System and Heterogeneous Integratio
 n with Passive TSV-Interposer (2.5D IC Integration) for artificial intelli
 gence applications\, and (e) Multiple System and Heterogeneous Integration
  with Active TSV-Interposer (3D IC Integration)\; (6) Summary\; (7) Trends
  in Chiplet Design and Heterogeneous Integration Packaging.\n\nSpeaker(s):
  John Lau\n\nBldg: Qualcomm Building Q\, 6455 Lusk Blvd\, (Building entry 
 details to be sent on March 12th)\, San Diego\, California\, United States
 \, 92121
LOCATION:Bldg: Qualcomm Building Q\, 6455 Lusk Blvd\, (Building entry detai
 ls to be sent on March 12th)\, San Diego\, California\, United States\, 92
 121
ORGANIZER:pthadesar@ieee.org
SEQUENCE:13
SUMMARY:Communications between Chiplets – Bridge 
URL;VALUE=URI:https://events.vtools.ieee.org/m/408907
X-ALT-DESC:Description: <br /><p><a name="_Hlk128301250"></a>Chiplet is a c
 hip design method and heterogeneous integration is a chip packaging method
 . Chiplet design and heterogeneous integration packaging have been generat
 ed lots of tractions lately. For the next few years\, we will see more imp
 lementations of a higher level of chiplet designs and heterogeneous integr
 ation packaging\, whether it is for cost\, time-to-market\, performance\, 
 form factor\, or power consumption. In this lecture\, the following topics
  will be covered: (1) System-on-Chip (SoC)\; (2) Why Chiplet Design\; (3) 
 Chiplet Design and Heterogeneous Integration Packaging (a) Chip Partition 
 and Chip Split\, (b) Chip partition and Heterogeneous Integration\, (c) Ch
 ip split and Heterogeneous Integration\, and (d) Advantages and Disadvanta
 ges\; (4) Lateral Communication between Chiplets (e.g.\, Bridges) (a) Brid
 ge Embedded in Build-up Package Substrate\, (b) Bridge Embedded in Fan-Out
  EMC with RDLs\, (c) UCIe\, and (d) Hybrid Bonding Bridge\; (5) Chiplet De
 sign and Heterogeneous Integration Packaging (a) Multiple System and Heter
 ogeneous Integration with Package Substrate (2D IC Integration)\, (b) Mult
 iple System and Heterogeneous Integration with Thin Film layer on the Pack
 age Substrate (2.1D IC Integration)\, (c) Multiple System and Heterogeneou
 s Integration with TSV-less (Organic) Interposer (2.3D IC Integration)\, (
 d) Multiple System and Heterogeneous Integration with Passive TSV-Interpos
 er (2.5D IC Integration) for artificial intelligence applications\, and (e
 ) Multiple System and Heterogeneous Integration with Active TSV-Interposer
  (3D IC Integration)\; (6) Summary\; (7) Trends in Chiplet Design and Hete
 rogeneous Integration Packaging.</p>
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