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DTSTART;TZID=America/New_York:20240319T130000
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DESCRIPTION:Abstract: 3D integration technology enables heterogeneous syste
 m scaling by offering higher I/O densities\, shorter interconnect lengths\
 , higher bandwidth and smaller form factors compared to 2D packaging solut
 ions. In recent years\, many products have been released taking advantage 
 of this technology to combine logic\, memory and imaging and/or optical co
 mponents into 3D stacked die\, or 2.5D interposer configurations. Due to t
 he vertical integration of thinned silicon chips\, the strong thermal coup
 ling between the tiers in the 3D stack\, and the difficulty to remove heat
  from within the 3D die stack\, thermal management is one of the major cha
 llenges of 3D integration technology. The incorporation of 3DIC and co-pac
 kaged optics on 2.5D interposer architectures to boost the compute through
 put\, has further complicated the cooling challenge.\n\nIn this talk\, the
  thermal impact of the recent scaling trends in 3D die and wafer stacking 
 and CPO\, including hybrid bonding\, backside power delivery\, and BEOL sc
 aling will be discussed. Furthermore\, the thermal opportunities of 3D fun
 ctional partitioning and advanced liquid cooling solutions\, to enable 2.5
 D HPC applications of multiple kW\, will be addressed.\n\nSpeaker(s): Dr. 
 Herman Oprins\n\nVirtual: https://events.vtools.ieee.org/m/411159
LOCATION:Virtual: https://events.vtools.ieee.org/m/411159
ORGANIZER:
SEQUENCE:12
SUMMARY:Thermal challenges and advanced cooling opportunities for 2.5D and 
 3D high performance computing
URL;VALUE=URI:https://events.vtools.ieee.org/m/411159
X-ALT-DESC:Description: <br /><p class="x_elementtoproof"><strong><span dat
 a-ogsc="black">Abstract</span></strong><span data-ogsc="black">:&nbsp\;</s
 pan><span data-ogsc="black">3D integration technology enables heterogeneou
 s system scaling by offering higher I/O densities\, shorter interconnect l
 engths\, higher bandwidth and smaller form factors compared to 2D packagin
 g solutions. In recent years\, many products have been released taking adv
 antage of this technology to combine logic\, memory and imaging and/or opt
 ical components into 3D stacked die\, or 2.5D interposer configurations. D
 ue to the vertical integration of thinned silicon chips\, the strong therm
 al coupling between the tiers in the 3D stack\, and the difficulty to remo
 ve heat from within the 3D die stack\, thermal management is one of the ma
 jor challenges of 3D integration technology. The incorporation of 3DIC and
  co-packaged optics on 2.5D interposer architectures to boost the compute 
 throughput\, has further complicated the cooling challenge.</span></p>\n<p
  class="x_elementtoproof"><span data-ogsc="black">In this talk\, the therm
 al impact of the recent scaling trends in 3D die and wafer stacking and CP
 O\, including hybrid bonding\, backside power delivery\, and BEOL scaling 
 will be discussed. Furthermore\, the thermal opportunities of 3D functiona
 l partitioning and advanced liquid cooling solutions\, to enable 2.5D HPC 
 applications of multiple kW\, will be addressed.</span></p>
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