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DTSTART:20240310T030000
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DTSTAMP:20240326T140115Z
UID:42F23D88-1CCA-4F4B-A6D3-4D23F98AFEF5
DTSTART;TZID=America/Los_Angeles:20240319T090000
DTEND;TZID=America/Los_Angeles:20240319T101500
DESCRIPTION:3D integration technology enables heterogeneous system scaling 
 by offering higher I/O densities\, shorter interconnect lengths\, higher b
 andwidth and smaller form factors compared to 2D packaging solutions. In r
 ecent years\, many products have been released taking advantage of this te
 chnology to combine logic\, memory and imaging and/or optical components i
 nto 3D stacked die\, or 2.5D interposer configurations. Due to the vertica
 l integration of thinned silicon chips\, the strong thermal coupling betwe
 en the tiers in the 3D stack\, and the difficulty to remove heat from with
 in the 3D die stack\, thermal management is one of the major challenges of
  3D integration technology. The incorporation of 3DIC and co-packaged opti
 cs on 2.5D interposer architectures to boost the compute throughput\, has 
 further complicated the cooling challenge.\nIn this talk\, the thermal imp
 act of the recent scaling trends in 3D die and wafer stacking and CPO\, in
 cluding hybrid bonding\, backside power delivery\, and BEOL scaling will b
 e discussed. Furthermore\, the thermal opportunities of 3D functional part
 itioning and advanced liquid cooling solutions\, to enable 2.5D HPC applic
 ations of multiple kW\, will be addressed.\n\nSpeaker(s): Herman Oprins\, 
 \n\nVirtual: https://events.vtools.ieee.org/m/411225
LOCATION:Virtual: https://events.vtools.ieee.org/m/411225
ORGANIZER:p.wesling@ieee.org
SEQUENCE:10
SUMMARY:Thermal challenges and advanced cooling opportunities for 2.5D and 
 3D high performance computing
URL;VALUE=URI:https://events.vtools.ieee.org/m/411225
X-ALT-DESC:Description: <br /><p>3D integration technology enables heteroge
 neous system scaling by offering higher I/O densities\, shorter interconne
 ct lengths\, higher bandwidth and smaller form factors compared to 2D pack
 aging solutions. In recent years\, many products have been released taking
  advantage of this technology to combine logic\, memory and imaging and/or
  optical components into 3D stacked die\, or 2.5D interposer configuration
 s. Due to the vertical integration of thinned silicon chips\, the strong t
 hermal coupling between the tiers in the 3D stack\, and the difficulty to 
 remove heat from within the 3D die stack\, thermal management is one of th
 e major challenges of 3D integration technology. The incorporation of 3DIC
  and co-packaged optics on 2.5D interposer architectures to boost the comp
 ute throughput\, has further complicated the cooling challenge.<br>In this
  talk\, the thermal impact of the recent scaling trends in 3D die and wafe
 r stacking and CPO\, including hybrid bonding\, backside power delivery\, 
 and BEOL scaling will be discussed. Furthermore\, the thermal opportunitie
 s of 3D functional partitioning and advanced liquid cooling solutions\, to
  enable 2.5D HPC applications of multiple kW\, will be addressed.</p>
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