BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Sao_Paulo BEGIN:DAYLIGHT DTSTART:20380119T001407 TZOFFSETFROM:-0300 TZOFFSETTO:-0300 RRULE:FREQ=YEARLY;BYDAY=3TU;BYMONTH=1 TZNAME:-03 END:DAYLIGHT BEGIN:STANDARD DTSTART:20190216T230000 TZOFFSETFROM:-0200 TZOFFSETTO:-0300 RRULE:FREQ=YEARLY;BYDAY=3SA;BYMONTH=2 TZNAME:-03 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20241228T185437Z UID:88214005-B82E-46E8-AC07-D95ECB170894 DTSTART;TZID=America/Sao_Paulo:20240417T140000 DTEND;TZID=America/Sao_Paulo:20240417T150000 DESCRIPTION:The transition from two-dimensional (2D) transistors to three-d imensional (3D) transistors at the beginning of the 21st century required the development of new models for 3D transistors. The work of developing m odels of semiconductor devices is a typical activity of the Academy\, whic h our group followed\, beginning the development of a new model for 3D Fin FET devices\, in 2006. These devices have a silicon fin\, surrounded by th ree gates\, two laterals and one on the top. The Si layer is narrow enough \, creating a potential distribution across its thickness\, where the pote ntial at the center is different from zero. Considering this potential dis tribution and the fact that the Si layer is doped\, lead to a transcendent al equation for the distribution of the electric field from gate to gate\, that has no direct analytical solution.\n\nIn this presentation we will s how an example of a compact\, continuous and analytical model known as Sym metric Doped Double-Gate Model (SDDGM)\, where the indicate problems were solved. The model was complemented with variable mobility\, the effects of short channel\, leakage currents and dependence on ambient temperature. I n addition\, it was demonstrated that this model can be used to model also recent 3D structures\, such as nanowires\, nanosheets and stacked nanoshe ets. Validation of the using this model for these new devices will be show n. SDDGM was implemented in the circuit simulator SmartSPICE\, using Veril og-A language.\n\nEven today\, the development of more precise models\, as well as complements for applying them to new devices\, is an open topic f or the Academy.\n\nCo-sponsored by: Centro Universitario FEI\n\nSpeaker(s) : Dr. Antonio Cerdeira\, \n\nCentro Universitario FEI\, Av. Humberto de A. C. Branco\, 3972\, Sao Bernardo do Campo\, Sao Paulo\, Brazil\, 09850901 LOCATION:Centro Universitario FEI\, Av. Humberto de A. C. Branco\, 3972\, S ao Bernardo do Campo\, Sao Paulo\, Brazil\, 09850901 ORGANIZER:pavanello@fei.edu.br SEQUENCE:15 SUMMARY:MODELING FINFETS\, NANOWIRES AND NANOSHEETS URL;VALUE=URI:https://events.vtools.ieee.org/m/412572 X-ALT-DESC:Description: <br /><p class="MsoNormal" style="margin-bottom: 0i n\; text-align: justify\; line-height: 150%\;"><span style="font-size: 14. 0pt\; line-height: 150%\; font-family: 'Times New Roman'\,serif\;"><span s tyle="mso-spacerun: yes\;">&nbsp\;&nbsp\; </span><span style="mso-spacerun : yes\;">&nbsp\;</span></span><span style="font-size: 12.0pt\; line-height : 150%\; font-family: 'Times New Roman'\,serif\;">The transition from two- dimensional (2D) transistors to three-dimensional (3D) transistors at the beginning of the 21st century required the development of new models for 3 D transistors. The work of developing models of semiconductor devices is a typical activity of the Academy\, which our group followed\, beginning th e development of a new model for 3D FinFET devices\, in 2006. These device s have a silicon fin\, surrounded by three gates\, two laterals and one on the top. The Si layer is narrow enough\, creating a potential distributio n across its thickness\, where the potential at the center is different fr om zero. Considering this potential distribution and the fact that the Si layer is doped\, lead to a transcendental equation for the distribution of the electric field from gate to gate\, that has no direct analytical solu tion. </span></p>\n<p class="MsoNormal" style="margin-bottom: 0in\; text-a lign: justify\; line-height: 150%\;"><span style="font-size: 12.0pt\; line -height: 150%\; font-family: 'Times New Roman'\,serif\;"><span style="mso- spacerun: yes\;">&nbsp\;&nbsp\;&nbsp\; </span>In this presentation we will show an example of a compact\, continuous and analytical model known as S ymmetric Doped Double-Gate Model (<em style="mso-bidi-font-style: normal\; ">SDDGM</em>)\, where the indicate problems were solved. The model was com plemented with variable mobility\, the effects of short channel\, leakage currents and dependence on ambient temperature. In addition\, it was demon strated that this model can be used to model also recent 3D structures\, s uch as nanowires\, nanosheets and stacked nanosheets. Validation of the us ing this model for these new devices will be shown. </span><em style="mso- bidi-font-style: normal\;"><span style="font-size: 12.0pt\; line-height: 1 50%\; font-family: 'Times New Roman'\,serif\; mso-fareast-font-family: Sim Sun\;">SDDGM</span></em><span style="font-size: 12.0pt\; line-height: 150% \; font-family: 'Times New Roman'\,serif\; mso-fareast-font-family: SimSun \;"> was implemented in the circuit simulator SmartSPICE\, using Verilog-A language.</span></p>\n<p class="MsoNormal" style="margin-bottom: 0in\; te xt-align: justify\; line-height: 150%\;"><span style="font-size: 12.0pt\; line-height: 150%\; font-family: 'Times New Roman'\,serif\;"><span style=" mso-spacerun: yes\;">&nbsp\;&nbsp\;&nbsp\; </span>Even today\, the develop ment of more precise models\, as well as complements for applying them to new devices\, is an open topic for the Academy.</span></p> END:VEVENT END:VCALENDAR