BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Sao_Paulo BEGIN:DAYLIGHT DTSTART:20380119T001407 TZOFFSETFROM:-0300 TZOFFSETTO:-0300 RRULE:FREQ=YEARLY;BYDAY=3TU;BYMONTH=1 TZNAME:-03 END:DAYLIGHT BEGIN:STANDARD DTSTART:20190216T230000 TZOFFSETFROM:-0200 TZOFFSETTO:-0300 RRULE:FREQ=YEARLY;BYDAY=3SA;BYMONTH=2 TZNAME:-03 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20241228T185332Z UID:8BA5A6DE-BFAA-41E4-A66A-D2E08CE49B73 DTSTART;TZID=America/Sao_Paulo:20240417T153000 DTEND;TZID=America/Sao_Paulo:20240417T163000 DESCRIPTION:The metal-oxide-semiconductor field effect transistor\, where s ilicon is the semiconductor material\, Si MOSFETs\, and their successors F INFETs and multigates devices (nanowires\, nanosheets\, stacked devices\, etc) are at present\, the basic semiconductor device allowing the tremendo us development reached by actual semiconductor industry to meet the requir ements of data processing\, artificial intelligence mobile devices and oth er techniques necessary for economic\, social\, and scientific development .\n\nTo achieve the required demands\, it has been necessary a constant re duction of the transistor size\, which has the prediction of Moore´s Law\ , of duplicating the number of transistors in a chip every two-three year. This miniaturization process has had to overcome important problems relat ed to parasitic effects present in bulk materials called short channel eff ects (SCEs). For example\, as the channel length is reduced\, the device c urrent in the below threshold regime will increase\, and so\, the static p ower consumed.\n\nHowever\, in bulk 3D semiconductors\, the reduction of x s\, increases the threshold voltage VT.\, due to the increase of defects a s dangling bonds and interface states at the interface of the semiconducto r/dielectric. At the same time\, mobility decreases as []xs6 due to the in crease in carrier scattering at the surface. In general\, for ultrathin 3D FETs\, the electrostatic control of carriers in the channel is reduced\, while the leakage current increases.\n\nOn the contrary\, in a two-dimensi onal (2D) material\, electrons can be naturally confined within a very thi n channel formed by few monoatomic layers\, where carriers can in principl e uniformly controlled by the gate voltage\, while the leakage current red uces.\n\nFor the above reasons\, during the last years\, much work has bee n done regarding the possibility of using 2D semiconductors to overcome th e above-mentioned limitations in further scaling of 3D semiconductor devic es. In this talk\, we will analyse some of these characteristics\, as well as results obtained in fabricating 2D semiconductor FETs\, using differen t methods. Finally\, we will present some work done on modelling these new devices\, already available and discuss challenges to overcome.\n\nCo-spo nsored by: Centro Universitario FEI\n\nSpeaker(s): Dr. Magali Estrada\, \n \nCentro Universitario FEI\, Av. Humberto de A. C. Branco\, 3972\, Sao Ber nardo do Campo\, Sao Paulo\, Brazil\, 09850901 LOCATION:Centro Universitario FEI\, Av. Humberto de A. C. Branco\, 3972\, S ao Bernardo do Campo\, Sao Paulo\, Brazil\, 09850901 ORGANIZER:pavanello@fei.edu.br SEQUENCE:10 SUMMARY:2D semiconductor FET transistors: Characteristics\, fabrication and modelling URL;VALUE=URI:https://events.vtools.ieee.org/m/412575 X-ALT-DESC:Description: <br /><p class="MsoNormal" style="margin-bottom: 0i n\; text-align: justify\; text-indent: 17.0pt\; line-height: normal\; mso- layout-grid-align: none\; text-autospace: none\;"><span lang="EN-GB" style ="font-size: 12.0pt\; font-family: 'Times New Roman'\,serif\; mso-ansi-lan guage: EN-GB\;">The metal-oxide-semiconductor field effect transistor\, wh ere silicon is the semiconductor material\, Si MOSFETs\, and their success ors FINFETs and multigates devices (nanowires\, nanosheets\, stacked devic es\, etc)</span><span lang="EN-GB" style="font-size: 12.0pt\; font-family: 'Arial'\,sans-serif\; mso-ansi-language: EN-GB\;"> </span><span lang="EN- GB" style="font-size: 12.0pt\; font-family: 'Times New Roman'\,serif\; mso -ansi-language: EN-GB\;">are at present\, the basic semiconductor device a llowing the tremendous development reached by actual semiconductor industr y to meet the requirements of data processing\, artificial intelligence mo bile devices and other techniques necessary for economic\, social\, and sc ientific development.</span></p>\n<p class="MsoNormal" style="margin-botto m: 0in\; text-align: justify\; text-indent: 17.0pt\; line-height: normal\; mso-layout-grid-align: none\; text-autospace: none\;"><span lang="EN-GB" style="font-size: 12.0pt\; font-family: 'Times New Roman'\,serif\; mso-ans i-language: EN-GB\;">To achieve the required demands\, it has been necessa ry a constant reduction of the transistor size\, which has the prediction of Moore&acute\;s Law\, of duplicating the number of transistors in a chip every two-three year. This miniaturization process has had to overcome im portant problems related to parasitic effects present in bulk materials ca lled short channel effects (SCEs). </span><span style="font-size: 12.0pt\; font-family: 'Times New Roman'\,serif\;">For example\, as the channel len gth is reduced\, the device current in the below threshold regime will inc rease\, and so\, the static power consumed. </span></p>\n<p class="MsoNorm al" style="margin-bottom: 0in\; text-align: justify\; text-indent: 17.0pt\ ; line-height: normal\; mso-layout-grid-align: none\; text-autospace: none \;"><span style="font-size: 12.0pt\; font-family: 'Times New Roman'\,serif \; mso-ligatures: none\;">However\, in bulk 3D semiconductors\, the reduct ion of&nbsp\;<em>x<sub>s\,</sub></em> increases the threshold voltage <em> V<sub>T.\, </sub></em>due to the increase of defects as dangling bonds and interface states at the interface of the semiconductor/dielectric.<em><su b> </sub></em>At the same time\,<em><sub> </sub></em>mobility decreases as <a name="_Hlk145533730"></a><em>x<sub>s</sub><sup>6</sup></em> due to the increase in carrier scattering at the surface. In general\, for ultrathin 3D FETs\, the electrostatic control of carriers in the channel is reduced \, while the leakage current increases. </span></p>\n<p class="MsoNormal" style="margin-bottom: 0in\; text-align: justify\; text-indent: 17.0pt\; li ne-height: normal\;"><span style="font-size: 12.0pt\; font-family: 'Times New Roman'\,serif\; mso-ligatures: none\;">On the contrary\, in a two-dime nsional (2D) material\, electrons can be naturally confined within a very thin channel formed by few monoatomic layers\, where carriers can in princ iple uniformly controlled by the gate voltage\, while the leakage current reduces.</span></p>\n<p class="MsoNormal" style="margin-bottom: 0in\; text -align: justify\; text-indent: 17.0pt\; line-height: normal\; mso-layout-g rid-align: none\; text-autospace: none\;"><span lang="EN-GB" style="font-s ize: 12.0pt\; font-family: 'Times New Roman'\,serif\; mso-ansi-language: E N-GB\;">For the above reasons\, during the last years\, much work has been done regarding the possibility of using 2D semiconductors to overcome the above-mentioned limitations in further scaling of 3D semiconductor device s. In this talk\, we will analyse some of these characteristics\, as well as results obtained in fabricating 2D semiconductor FETs\, using different methods. Finally\, we will present some work done on modelling these new devices\, already available and discuss challenges to overcome.</span></p> END:VEVENT END:VCALENDAR