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PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
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TZID:Asia/Kolkata
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DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
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BEGIN:VEVENT
DTSTAMP:20260126T171655Z
UID:354467D5-6C5F-428A-B02C-41C35799D578
DTSTART;TZID=Asia/Kolkata:20240227T090000
DTEND;TZID=Asia/Kolkata:20240228T180000
DESCRIPTION:A two-day workshop on Chip Design using Cadence Tools was condu
 cted by the PACE IEEE Student Branch and IEEE CEDA in the Department of EC
 E on February 27 and 28. The workshop was successfully completed under the
  coordination of Dr. Zakir B.\, Associate Professor. The resource person f
 or the workshop was Mr. P Rajendra from Entuple Technologies\, Bangalore.\
 n\nThis workshop is designed to provide participants with a comprehensive 
 understanding of the latest advancements in chip design technology\, equip
 ping them with the skills and knowledge necessary to excel in this rapidly
  evolving field.\n\nCo-sponsored by: Mangalore Sub Section\n\nSpeaker(s): 
 Raj\, \n\nAgenda: \nWorkshop Highlights:\n\nDay 1: Introduction to Cadence
  Tools and Basic Concepts\nOverview of Cadence tool suite\nUnderstanding t
 he fundamentals of chip design\nHands-on experience with Cadence tools for
  schematic entry and simulation\nIntroduction to layout design and physica
 l verification\n\nDay 2: Advanced Topics and Practical Applications\nSigna
 l integrity and power analysis\nHigh-speed design considerations\nIntroduc
 tion to analog and mixed-signal design\nCase studies and real-world applic
 ations\, finally\nQ&A and interactive sessions.\n\nP A College of Engineer
 ing\, Mangalore\, Karnataka\, India\, 574153
LOCATION:P A College of Engineering\, Mangalore\, Karnataka\, India\, 57415
 3
ORGANIZER:mdzakir87@gmail.com
SEQUENCE:66
SUMMARY:Two days' workshop on chip design using Cadence tools
URL;VALUE=URI:https://events.vtools.ieee.org/m/414442
X-ALT-DESC:Description: <br /><div dir="auto">A two-day workshop on Chip De
 sign using Cadence Tools was conducted by the PACE IEEE Student Branch and
  IEEE CEDA in the Department of ECE on February 27 and 28. The workshop wa
 s successfully completed under the coordination of Dr. Zakir B.\, Associat
 e Professor. The resource person for the workshop was Mr. P Rajendra from 
 Entuple Technologies\, Bangalore.</div>\n<div dir="auto">&nbsp\;</div>\n<d
 iv dir="auto">This workshop is designed to provide participants with a com
 prehensive understanding of the latest advancements in chip design technol
 ogy\, equipping them with the skills and knowledge necessary to excel in t
 his rapidly evolving field.</div>\n<div dir="auto">&nbsp\;</div>\n<div dir
 ="auto"><img src="https://ieee-ceda.org/sites/ieeeceda/files/styles/cc_con
 tainer/public/images/WorkShopPAC_0.jpg?itok=Kbr88Cot"></div><br /><br />Ag
 enda: <br /><div dir="auto">Workshop Highlights:</div>\n<div dir="auto">&n
 bsp\;</div>\n<div dir="auto">Day 1: Introduction to Cadence Tools and Basi
 c Concepts</div>\n<div dir="auto">Overview of Cadence tool suite</div>\n<d
 iv dir="auto">Understanding the fundamentals of chip design</div>\n<div di
 r="auto">Hands-on experience with Cadence tools for schematic entry and si
 mulation</div>\n<div dir="auto">Introduction to layout design and physical
  verification</div>\n<div dir="auto">&nbsp\;</div>\n<div dir="auto">Day 2:
  Advanced Topics and Practical Applications</div>\n<div dir="auto">Signal 
 integrity and power analysis</div>\n<div dir="auto">High-speed design cons
 iderations</div>\n<div dir="auto">Introduction to analog and mixed-signal 
 design</div>\n<div dir="auto">Case studies and real-world applications\, f
 inally&nbsp\;</div>\n<div dir="auto">Q&amp\;A and interactive sessions.</d
 iv>
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