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DTSTART:20240310T030000
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DTSTART:20241103T010000
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DTSTAMP:20240506T011632Z
UID:85EADE76-2E65-4C05-AF1E-0BA0F892FE17
DTSTART;TZID=America/New_York:20240430T120000
DTEND;TZID=America/New_York:20240430T130000
DESCRIPTION:The next-generation wireline and wireless systems promise wider
  bandwidth to enable a vast range of applications\, including autonomous v
 ehicles\, virtual reality\, and the internet of things.\n\nSuch high data 
 rates mandate precise clock generation to meet the timing budget. At the s
 ame time\, flexibility to support multiple standards and scalability to me
 et higher integration density introduces additional dimensions to the cloc
 king challenge. This talk will discuss recent circuit and architecture inn
 ovations to address these challenges. Starting from simple phase-locking c
 oncepts such as PLL\, DLL and ILO\, this talk will explain how the combina
 tion of these techniques is adopted in modern communication systems.\n\nIt
  will also describe two example cases:\n\ni. A 28 GHz frequency synthesize
 r for 5G LO based beam forming\, and\n\nii. A flexible clocking solution f
 or 10Gb/s to 112 Gb/s SerDes in 7 nm finFET technology.\n\nSpeaker(s): \, 
 Prof. Masum Hossain\n\nBldg: Hub 350\, 350 Legget Dr\, Kanata\, Ontario\, 
 Canada\, K2K 0G7
LOCATION:Bldg: Hub 350\, 350 Legget Dr\, Kanata\, Ontario\, Canada\, K2K 0G
 7
ORGANIZER:aabdella@ieee.org
SEQUENCE:15
SUMMARY:Low-jitter Flexible Frequency Generation for Next-Generation Commun
 ication Systems
URL;VALUE=URI:https://events.vtools.ieee.org/m/417903
X-ALT-DESC:Description: &lt;br /&gt;&lt;p class=&quot;MsoNormal&quot;&gt;&lt;img style=&quot;display: blo
 ck\; margin-left: auto\; margin-right: auto\;&quot; src=&quot;https://events.vtools.
 ieee.org/vtools_ui/media/display/b5540f84-d4a5-4bdd-b5b7-c42e16e4e9db&quot; wid
 th=&quot;548&quot; height=&quot;308&quot;&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot;&gt;The next-generation wirel
 ine and wireless systems promise wider bandwidth to enable a vast range of
  applications\, including autonomous vehicles\, virtual reality\, and the 
 internet of things.&amp;nbsp\;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot;&gt;Such high data rates 
 mandate precise clock generation to meet the timing budget. At the same&amp;nb
 sp\;time\, flexibility to support multiple standards and scalability to me
 et higher integration density&amp;nbsp\;introduces additional dimensions to th
 e clocking challenge. This talk will discuss recent circuit&amp;nbsp\;and arch
 itecture innovations to address these challenges. Starting from simple pha
 se-locking&amp;nbsp\;concepts such as PLL\, DLL and ILO\, this talk will expla
 in how the combination of these&amp;nbsp\;techniques is adopted in modern comm
 unication systems.&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot;&gt;It will also describe two exa
 mple&amp;nbsp\;cases:&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot;&gt;i. A 28 GHz frequency synthesi
 zer for 5G LO based beam forming\, and&amp;nbsp\;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot;&gt;ii
 . A flexible&amp;nbsp\;clocking solution for 10Gb/s to 112 Gb/s SerDes in 7 nm
  finFET technology.&lt;/p&gt;
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