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DTSTART:20380119T091407
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DTSTART:20091231T230000
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BEGIN:VEVENT
DTSTAMP:20161101T171308Z
UID:1C605F61-A056-11E6-A7C6-0050568D7F66
DTSTART;TZID=Asia/Dhaka:20161025T100000
DTEND;TZID=Asia/Dhaka:20161027T154000
DESCRIPTION:Workshop objective:\n\nThe aim of this workshop is to provide h
 ands-on experience on the state-of-the-art Cadence EDA tools for VLSI Desi
 gn. The participants will have an exposure to the Circuit Design &amp; Simulat
 ion\, Layout\, Physical Verification (DRC\, LVS)\, and Extraction. The wor
 kshop includes practice sessions on the Cadence design and simulation tool
 s (Virtuoso\, Spectre\, Assura and Incisive).\n\nAbout Cadence:\n\nCadence
  is a leading provider of EDA and semiconductor IP. Our custom/analog tool
 s help engineers design the transistors\, standard cells\, and IP blocks t
 hat make up SoCs. Our digital tools automate the design and verification o
 f giga-scale\, giga-hertz SoCs at the latest semiconductor processing node
 s. Our IC packaging and PCB tools permit the design of complete boards and
  subsystems. Cadence also offers a growing portfolio of design IP and veri
 fication IP for memories\, interface protocols\, analog/mixed-signal compo
 nents\, and specialized processors. And reaching up to the systems level\,
  Cadence offers an integrated suite of hardware/software co-development pl
 atforms. In short\, Cadence® technology helps customers build great produ
 cts that connect the world.\n\nWorkshop Topics:\n\n-  Introduction to VLSI
 \, Technologies\, Applications\, Future Trends in VLSI.\n-  Design and Ana
 lysis of Analog Circuits.\n-  Design and Analysis of Digital Circuits.\n- 
  Design of Layouts of Analog and Digital Circuits.\n\nAbout the participan
 ts:\n\nNumber of participants: 19\n\nWorkshop Process:\n\nThe program invo
 lves individual and group exercises as well as input from the course leade
 r\, and presentations from the speakers. There were many opportunities to 
 raise questions or concerns throughout the Workshops.\n\nThe following app
 roaches were used\n\n-  Lectures\n-  Discussions\n-  Group work which cons
 tituted a means for developing the skills of participants.\n-  Practice se
 ssions\n\nDay-1 or 25.10.2016:\n\nFN: The workshop session started at 10:0
 0am with a brief lecture on history and invention of transistors\, IC’s 
 integration to VLSI technology\, VLSI design flow\, VLSI Design Styles\, t
 he design issues and design methodologies followed by Trends and future sc
 ope in VLSI.\n\nAN: The session started by giving an introduction to diffe
 rent EDA Tools and discussed the importance of Cadence EDA tool. There aft
 er tool was introduced to the participants with the design of basic invert
 er and then the students have simulated the circuit using spectre and done
  different analysis transient\, DC\, AC etc. Also the participants have ob
 served the characteristics of transistors by changing different parameters
  like W/L ratios and variations in biasing the circuit etc.\n\nDay-2 or 26
 -10-16:\n\nFN: The session started with a lecture on fundamentals of analo
 g signals and system\, and the design and analysis of different analog cir
 cuit. Followed by the design entry in virtuoso (Schematic editor).\n\nAN: 
 In this session the students have simulated the circuit using spectre and 
 done different analysis transient\, DC\, AC etc. Also the participants hav
 e observed the characteristics of transistors by changing different parame
 ters like W/L ratios and variations in biasing the circuit etc.\n\nDay-3 o
 r 27.10.2016:\n\nFN: The session was started by introducing the Custom IC 
 Flow\, and the design rules for 180nm technology\, followed by the introdu
 ction to stick diagrams and Layouts. And the participants have done the la
 yout for an inverter without design violations.\n\nAN: This session was de
 dicated for LVS and RC extraction and followed by the post layout simulati
 on of inverter. After layout simulation the results are compared with the 
 schematic results.\n\nHyderabad\, Andhra Pradesh\, India
LOCATION:Hyderabad\, Andhra Pradesh\, India
ORGANIZER:aindala.prashanthi@gmail.com
SEQUENCE:1
SUMMARY:a 3 day workshop on&quot;vlsi design using cadence EDA Tool&quot;
URL;VALUE=URI:https://events.vtools.ieee.org/m/41959
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;&lt;strong&gt;Workshop objective: &lt;/strong&gt;&lt;/p&gt;\
 n&lt;p&gt;The aim of this workshop is to provide hands-on experience on the stat
 e-of-the-art Cadence EDA tools for VLSI Design. The participants will have
  an exposure to the Circuit Design &amp;amp\; Simulation\, Layout\, Physical V
 erification (DRC\, LVS)\, and Extraction. The workshop includes practice s
 essions on the Cadence design and simulation tools (Virtuoso\, Spectre\, A
 ssura and Incisive).&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;About Cadence:&lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;Caden
 ce is a leading provider of EDA and semiconductor IP. Our custom/analog to
 ols help engineers design the transistors\, standard cells\, and IP blocks
  that make up SoCs. Our digital tools automate the design and verification
  of giga-scale\, giga-hertz SoCs at the latest semiconductor processing no
 des. Our IC packaging and PCB tools permit the design of complete boards a
 nd subsystems. Cadence also offers a growing portfolio of design IP and ve
 rification IP for memories\, interface protocols\, analog/mixed-signal com
 ponents\, and specialized processors. And reaching up to the systems level
 \, Cadence offers an integrated suite of hardware/software co-development 
 platforms. In short\, Cadence&amp;reg\; technology helps customers build great
  products that connect the world.&lt;/p&gt;\n&lt;p&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;Workshop
  Topics:&lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;&amp;nbsp\;&lt;/strong&gt;&lt;/p&gt;\n&lt;ul&gt;\n&lt;li&gt;&amp;nbsp\; 
 Introduction to VLSI\, Technologies\, Applications\, Future Trends in VLSI
 .&lt;/li&gt;\n&lt;li&gt;&amp;nbsp\; Design and Analysis of Analog Circuits.&lt;/li&gt;\n&lt;li&gt;&amp;nbs
 p\; Design and Analysis of Digital Circuits.&lt;/li&gt;\n&lt;li&gt;&amp;nbsp\; Design of L
 ayouts of Analog and Digital Circuits.&lt;/li&gt;\n&lt;/ul&gt;\n&lt;p&gt;&lt;strong&gt;&amp;nbsp\;&lt;/st
 rong&gt;&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;&amp;nbsp\;&lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;&amp;nbsp\;&lt;/strong&gt;&lt;/p
 &gt;\n&lt;p&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;About the participants:&lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;Num
 ber of participants: 19&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;Workshop Process:&lt;/strong&gt;&lt;/p&gt;\n&lt;p
 &gt;The program involves individual and group exercises as well as input from
  the course leader\, and presentations from the speakers. There were many 
 opportunities to raise questions or concerns throughout the Workshops.&lt;/p&gt;
 \n&lt;p&gt;The following approaches were used&lt;/p&gt;\n&lt;ul&gt;\n&lt;li&gt;&amp;nbsp\;&amp;nbsp\;&amp;nbsp
 \;&amp;nbsp\;&amp;nbsp\;&amp;nbsp\;&amp;nbsp\;&amp;nbsp\; Lectures&lt;/li&gt;\n&lt;li&gt;&amp;nbsp\;&amp;nbsp\;&amp;nb
 sp\;&amp;nbsp\;&amp;nbsp\;&amp;nbsp\;&amp;nbsp\;&amp;nbsp\; Discussions&lt;/li&gt;\n&lt;li&gt;&amp;nbsp\;&amp;nbsp
 \;&amp;nbsp\;&amp;nbsp\;&amp;nbsp\;&amp;nbsp\;&amp;nbsp\;&amp;nbsp\; Group work which constituted 
 a means for developing the skills of participants.&lt;/li&gt;\n&lt;li&gt;&amp;nbsp\;&amp;nbsp\
 ;&amp;nbsp\;&amp;nbsp\;&amp;nbsp\;&amp;nbsp\;&amp;nbsp\;&amp;nbsp\; Practice sessions&lt;/li&gt;\n&lt;/ul&gt;\
 n&lt;p&gt;&lt;strong&gt;&amp;nbsp\;&lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;Day-1 or 25.10.2016:&lt;/strong&gt;
 &lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;FN:&lt;/strong&gt; The workshop session started at 10:00am with
  a brief lecture on history and invention of transistors\, IC&amp;rsquo\;s int
 egration to VLSI technology\, VLSI design flow\, VLSI Design Styles\, the 
 design issues and design methodologies followed by Trends and future scope
  in VLSI.&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;AN: &lt;/strong&gt;The session started by giving an in
 troduction to different EDA Tools and discussed the importance of Cadence 
 EDA tool. There after tool was introduced to the participants with the des
 ign of basic inverter and then the &amp;nbsp\;students have simulated the circ
 uit using spectre and done different analysis transient\, DC\, AC etc.&amp;nbs
 p\; Also the participants have observed the characteristics of transistors
  by changing different parameters like W/L ratios and variations in biasin
 g the circuit etc.&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;Day-2 or 26-10-16:&lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;&lt;st
 rong&gt;FN: &lt;/strong&gt;The session started with a lecture on fundamentals of an
 alog signals and system\, and the design and analysis of different analog 
 circuit. Followed by the design entry in virtuoso (Schematic editor).&lt;/p&gt;\
 n&lt;p&gt;&amp;nbsp\;&lt;strong&gt;AN: &lt;/strong&gt;In this session the students have simulate
 d the circuit using spectre and done different analysis transient\, DC\, A
 C etc. &amp;nbsp\;Also the participants have observed the characteristics of t
 ransistors by changing different parameters like W/L ratios and variations
  in biasing the circuit etc.&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;Day-3 or 27.10.2016:&lt;/strong&gt;
 &lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;FN:&lt;/strong&gt; The session was started by introducing the C
 ustom IC Flow\, and the design rules for 180nm technology\, followed by th
 e introduction to stick diagrams and Layouts. And the participants have do
 ne the layout for an inverter without design violations.&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;A
 N: &lt;/strong&gt;This session was dedicated for LVS and RC extraction and follo
 wed by the post layout simulation of inverter. After layout simulation the
  results are compared with the schematic results.&lt;/p&gt;
END:VEVENT
END:VCALENDAR