BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20240310T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20241103T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250204T045008Z UID:BE3F7EC4-4526-4D8E-8563-3DA0A443BE7C DTSTART;TZID=America/Los_Angeles:20240520T170000 DTEND;TZID=America/Los_Angeles:20240520T183000 DESCRIPTION:Speaker: Chris Cheng\, Distinguished Technologist\, Hewlett Pac kard Enterprise\n\nAbstract:\nGenerative AI and Large language models (LLM ) with domain knowledge enhancements will fundamentally change the way we design hardware. In this talk we will start with the basic concept of tran sformer with encoder and decoder. We will discuss how domain knowledge can be injected into LLM through retrieval augmented generation (RAG) and fin e tuning. We will also discuss the concept of LLM agent where complex desi gn tasks can be done by the agent through planning\, action with other too ls and reasoning. An even more advanced technique will involve the LLM opt imizing a design through optimization by prompt. We will conclude with the concept of foundational models for signal integrity and power integrity a s an example of how we can tie LLM and Generative AI to complete a complex engineering design task.\n\nSpeaker Bio:\nChris Cheng is a Distinguished Technologist at the Storage Division of Hewlett-Packard Enterprise. He is responsible for managing all high speed\, analog/mixed signal designs and hardware machine learning development within the Storage Division. He also held senior engineering positions in SUN Microsystems where he developed the original GTL system bus with Bill Gunning. He was a Principal Engineer in Intel where he led high speed processor bus design team. He was the fi rst hardware engineer in 3PAR and guided their high-speed design effort un til it was acquired by Hewlett Packard.\n\nRoom: SCDI 3301\, Bldg: Sobrato Campus for Discovery and Innovation\, 500 El Camino Real\, Santa Clara\, California\, United States\, 95053 LOCATION:Room: SCDI 3301\, Bldg: Sobrato Campus for Discovery and Innovatio n\, 500 El Camino Real\, Santa Clara\, California\, United States\, 95053 ORGANIZER:geochen1@yahoo.com SEQUENCE:17 SUMMARY:Large Language Models and Generative AI for High Performance System s URL;VALUE=URI:https://events.vtools.ieee.org/m/420026 X-ALT-DESC:Description: <br /><div dir="ltr"><strong>Speaker: </strong>Chri s Cheng\, Distinguished Technologist\, Hewlett Packard Enterprise</div>\n< div dir="ltr">\n<div>&nbsp\;</div>\n<div>&nbsp\;</div>\n<div><strong>Abstr act:</strong></div>\n<div>&nbsp\; &nbsp\; Generative AI and Large language models (LLM) with domain knowledge enhancements will fundamentally change the way we design hardware. In this talk we&nbsp\;will start with the bas ic concept of transformer with encoder and decoder. We will&nbsp\;discuss how domain knowledge can be injected into LLM through retrieval augmented& nbsp\;generation (RAG) and fine tuning. We will also discuss the concept o f LLM agent where&nbsp\;complex design tasks can be done by the agent thro ugh planning\, action with other&nbsp\;tools and reasoning. An even more a dvanced technique will involve the LLM optimizing&nbsp\;a design through o ptimization by prompt. We will conclude with the concept of&nbsp\;foundati onal models for signal integrity and power integrity as an example of how we&nbsp\;can tie LLM and Generative AI to complete a complex engineering d esign task.</div>\n<div>&nbsp\;</div>\n<div>&nbsp\;</div>\n</div>\n<div di r="ltr"><strong>Speaker Bio:</strong></div>\n<div>&nbsp\; &nbsp\; <strong> Chris Cheng</strong> is a Distinguished Technologist at the Storage Divisi on of Hewlett-Packard Enterprise. He is responsible for managing all high speed\, analog/mixed signal designs and hardware machine learning developm ent within the Storage Division. He also held senior engineering positions in SUN Microsystems where he developed the original GTL system bus with B ill Gunning. He was a Principal Engineer in Intel where he led high speed processor bus design team. He was the first hardware engineer in 3PAR and guided their high-speed design effort until it was acquired by Hewlett Pac kard.</div>\n<p>&nbsp\;</p> END:VEVENT END:VCALENDAR