BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20240310T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20241103T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20240601T161058Z UID:234E0C75-AF9A-48EA-A3C0-FB9D2B3B43C8 DTSTART;TZID=America/Los_Angeles:20240529T110000 DTEND;TZID=America/Los_Angeles:20240529T120000 DESCRIPTION:Antennas are integral part of wireless communication devices an d traditionally have remained off the Integrated Circuits (ICs which are a lso commonly known as chips) resulting in large sized modules. In the last decade\, the increased level of integration provided by silicon technolog ies and emerging applications at millimeter wave frequencies (such as 5G/6 G) has helped to achieve true System-on-Chip solutions bringing the antenn as on the chip. This is because antenna sizes at these frequencies become small enough for practical on-chip realization. Though\, there are a numbe r of benefits of putting antennas on-chip\, such as monolithic integration resulting in compact systems\, robustness due to absence of bond wires or other connection mechanisms between the antenna and the circuits\, lower cost due to mass manufacturing in standard CMOS processes\, etc. However\, there are a number of challenges to overcome\, for instance dealing with silicon substrate high conductivity and permittivity (resulting in poor ra diation efficiency)\, metal stack-up and layout restrictions\, and on-chip characterization through delicate probes\, etc. Furthermore\, the co-desi gn of circuits and antenna\, which sometime have contradicting requirement s\, need knowledge of both the domains. This talk aims to discuss the abov e challenges in detail as well as the proposed solutions. In particular\, many design examples will be shown for the gain and radiation efficiency e nhancement of on-chip antennas through artificial magnetic conductors. The talk will conclude with the upcoming trends in the field of on-chip anten nas.\n\nCo-sponsored by: University of Washington - Electrical and Compute r Engineering Department\, Washington State University - Electrical and Co mputer Engineering Department\n\nSpeaker(s): Prof. Atif Shamim\, \n\nVirtu al: https://events.vtools.ieee.org/m/420398 LOCATION:Virtual: https://events.vtools.ieee.org/m/420398 ORGANIZER:m.sharawi@ieee.org SEQUENCE:10 SUMMARY:On-Chip Antennas: The Last Barrier to True RF System-on-Chip URL;VALUE=URI:https://events.vtools.ieee.org/m/420398 X-ALT-DESC:Description: <br /><p class="MsoNormal" style="text-align: justi fy\;"><span lang="EN-US" style="font-family: 'Calibri'\,sans-serif\; mso-a scii-theme-font: minor-latin\; mso-hansi-theme-font: minor-latin\; mso-bid i-font-family: 'Times New Roman'\;">Antennas are integral part of wireless communication devices and traditionally have remained off the Integrated Circuits (ICs which are also commonly known as chips) resulting in large s ized modules. In the last decade\, the increased level of integration prov ided by silicon technologies and emerging applications at millimeter wave frequencies (such as 5G/6G) has helped to achieve true System-on-Chip solu tions bringing the antennas on the chip. This is because antenna sizes at these frequencies become small enough for practical on-chip realization. T hough\, there are a number of benefits of putting antennas on-chip\, such as monolithic integration resulting in compact systems\, robustness due to absence of bond wires or other connection mechanisms between the antenna and the circuits\, lower cost due to mass manufacturing in standard CMOS p rocesses\, etc. However\, there are a number of challenges to overcome\, f or instance dealing with silicon substrate high conductivity and permittiv ity (resulting in poor radiation efficiency)\, metal stack-up and layout r estrictions\, and on-chip characterization through delicate probes\, etc. Furthermore\, the co-design of circuits and antenna\, which sometime have contradicting requirements\, need knowledge of both the domains.<span styl e="mso-spacerun: yes\;">&nbsp\; </span>This talk aims to discuss the above challenges in detail as well as the proposed solutions. In particular\, m any design examples will be shown for the gain and radiation efficiency en hancement of on-chip antennas through artificial magnetic conductors. The talk will conclude with the upcoming trends in the field of on-chip antenn as. </span></p> END:VEVENT END:VCALENDAR