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DTSTAMP:20240621T210105Z
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DTSTART;TZID=America/New_York:20240618T200000
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DESCRIPTION:Advancements in technology scaling have ushered in larger syste
 ms boasting enhanced functionality\, increased operational speed\, and exp
 anded data bandwidth. However\, these benefits come with more demanding cl
 ocking requirements\, including extended distribution distances and height
 ened timing precision. Furthermore\, technology scaling has rendered tradi
 tional analog design challenging. Wider PVT variations necessitate intensi
 ve calibration efforts\, and increased integration levels call for resilie
 nce against external noise sources. Moreover\, the fact that reference fre
 quency and loop bandwidth do not scale at the same rate as technology lead
 s to prohibitive costs for oversized loop filters. While pure analog imple
 mentations offer intuitive operation and elegant analysis\, clocking circu
 its incorporating digital elements offer effective solutions to these chal
 lenges.\n\nThis presentation will cover how digital circuits can enhance c
 lock generation and distribution through techniques like calibration and s
 ignal processing. Beginning with well-established methods that harness the
  mixed-signal nature of PLLs\, such as delta-sigma modulation for the MDD 
 in fractional-N PLLs\, the presentation will shift toward digital-intensiv
 e architectures. It will focus on techniques that leverage digital impleme
 ntations for error detection and enhance timing accuracy through either an
 alog or digital correction. State-of-the-art designs featuring runtime cal
 ibration and power noise cancellation for clock generation and distributio
 n will also be introduced. This talk will conclude with insights into futu
 re challenges and trends.\n\nSpeaker(s): \, Ping-Hsuan Hsieh\n\nAgenda: \n
 8pm - 9pm : DL and Q/A\n\nVirtual: https://events.vtools.ieee.org/m/420963
LOCATION:Virtual: https://events.vtools.ieee.org/m/420963
ORGANIZER:bshubha@ieee.org
SEQUENCE:12
SUMMARY:IEEE PCJS SSCS DL : Dr Hsieh : “Digitally Enhanced Clock Generati
 on and Distribution”
URL;VALUE=URI:https://events.vtools.ieee.org/m/420963
X-ALT-DESC:Description: <br /><p>Advancements in technology scaling have us
 hered in larger systems boasting enhanced functionality\, increased operat
 ional speed\, and expanded data bandwidth. However\, these benefits come w
 ith more demanding clocking requirements\, including extended distribution
  distances and heightened timing precision. Furthermore\, technology scali
 ng has rendered traditional analog design challenging. Wider PVT variation
 s necessitate intensive calibration efforts\, and increased integration le
 vels call for resilience against external noise sources. Moreover\, the fa
 ct that reference frequency and loop bandwidth do not scale at the same ra
 te as technology leads to prohibitive costs for oversized loop filters. Wh
 ile pure analog implementations offer intuitive operation and elegant anal
 ysis\, clocking circuits incorporating digital elements offer effective so
 lutions to these challenges.</p>\n<p>This presentation will cover how digi
 tal circuits can enhance clock generation and distribution through techniq
 ues like calibration and signal processing. Beginning with well-establishe
 d methods that harness the mixed-signal nature of PLLs\, such as delta-sig
 ma modulation for the MDD in fractional-N PLLs\, the presentation will shi
 ft toward digital-intensive architectures. It will focus on techniques tha
 t leverage digital implementations for error detection and enhance timing 
 accuracy through either analog or digital correction. State-of-the-art des
 igns featuring runtime calibration and power noise cancellation for clock 
 generation and distribution will also be introduced. This talk will conclu
 de with insights into future challenges and trends.</p><br /><br />Agenda:
  <br /><p>8pm - 9pm : DL and Q/A</p>
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