BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20260126T171800Z
UID:85247DA3-0442-4372-8B60-357739C1C64B
DTSTART;TZID=Asia/Kolkata:20240508T090000
DTEND;TZID=Asia/Kolkata:20240508T180000
DESCRIPTION:IEEE CEDA Bangalore started a CoE at VIT. To support the studen
 ts\, we have organized one-day workshop on chip design. We have showed the
 m about how to install open-source CAD infrastructure in a desktop or Lapt
 op computer. Then we have guided them to get started with their first digi
 tal design. We finished PWM design. Then simulated and verified the result
 s using open-source tools.\n\nSpeaker(s): Aloke\, \n\nAgenda: \nIntroducti
 on to EDA tools\n\nInstalling virtual machine\n\nInstalling ubuntu\n\nInst
 alling iverilog\, yosys and gtkwave\n\nCoding combinational design in Veri
 log\n\nCoding sequential design in Verilog\n\nCombining sequential and com
 binational designs into PWM IP\n\nRoom: Seminar Hall\, Koramangala\, Banga
 lore\, Karnataka\, India\, 560034
LOCATION:Room: Seminar Hall\, Koramangala\, Bangalore\, Karnataka\, India\,
  560034
ORGANIZER:aloke.das@ieee.org
SEQUENCE:51
SUMMARY:Digital circuit design with open-source tools
URL;VALUE=URI:https://events.vtools.ieee.org/m/421054
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;IEEE CEDA Bangalore started a CoE at VIT. 
 To support the students\, we have organized one-day workshop on chip desig
 n. We have showed them about how to install open-source CAD infrastructure
  in a desktop or Laptop computer. Then we have guided them to get started 
 with their first digital design. We finished PWM design. Then simulated an
 d verified the results using open-source tools.&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br
  /&gt;&lt;p&gt;Introduction to EDA tools&lt;/p&gt;\n&lt;p&gt;Installing virtual machine&lt;/p&gt;\n&lt;p
 &gt;Installing ubuntu&lt;/p&gt;\n&lt;p&gt;Installing iverilog\, yosys and gtkwave&lt;/p&gt;\n&lt;p
 &gt;Coding combinational design in Verilog&lt;/p&gt;\n&lt;p&gt;Coding sequential design i
 n Verilog&lt;/p&gt;\n&lt;p&gt;Combining sequential and combinational designs into PWM 
 IP&lt;/p&gt;
END:VEVENT
END:VCALENDAR