BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20260126T171808Z
UID:78579B1D-1F3E-4391-A471-E7D3E56CBAA1
DTSTART;TZID=Asia/Kolkata:20240509T090000
DTEND;TZID=Asia/Kolkata:20240509T180000
DESCRIPTION:EEE CEDA Bangalore started a CoE at VIT. To support the student
 s\, we have organized one-day workshop on chip design. We have showed them
  about how to install open-source CAD infrastructure in a desktop or Lapto
 p computer. Then we have guided them to get started with their first analo
 g design. We finished op-amp design. Then simulated and verified the resul
 ts using open-source tools.\n\nSpeaker(s): Sarfraz\n\nAgenda: \nIntroducti
 on to analog open-source tools\n\nInstalling them in desktop and laptop\n\
 nCreating first circuit in LTspice\n\nSimulating in LTspice\n\nAnalog layo
 ut in Electric\n\nExtracting parasitic for 180 nm PDK\n\nCharacterizing op
 -amp\n\nRoom: Seminar Hall\, Koramangala\, Bangalore\, Karnataka\, India\,
  560034
LOCATION:Room: Seminar Hall\, Koramangala\, Bangalore\, Karnataka\, India\,
  560034
ORGANIZER:aloke.das@ieee.org
SEQUENCE:22
SUMMARY:Analog circuit design with open-source tools
URL;VALUE=URI:https://events.vtools.ieee.org/m/421057
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;EEE CEDA Bangalore started a CoE at VIT. T
 o support the students\, we have organized one-day workshop on chip design
 . We have showed them about how to install open-source CAD infrastructure 
 in a desktop or Laptop computer. Then we have guided them to get started w
 ith their first analog design. We finished op-amp design. Then simulated a
 nd verified the results using open-source tools.&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;b
 r /&gt;&lt;p&gt;Introduction to analog open-source tools&lt;/p&gt;\n&lt;p&gt;Installing them in
  desktop and laptop&lt;/p&gt;\n&lt;p&gt;Creating first circuit in LTspice&lt;/p&gt;\n&lt;p&gt;Simu
 lating in LTspice&lt;/p&gt;\n&lt;p&gt;Analog layout in Electric&lt;/p&gt;\n&lt;p&gt;Extracting par
 asitic for 180 nm PDK&lt;/p&gt;\n&lt;p&gt;Characterizing op-amp&amp;nbsp\;&lt;/p&gt;
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