BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Zurich BEGIN:DAYLIGHT DTSTART:20240331T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20241027T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20240909T122643Z UID:9C91B7F3-1EBE-439E-864F-FB2B060B235B DTSTART;TZID=Europe/Zurich:20240906T130000 DTEND;TZID=Europe/Zurich:20240906T170000 DESCRIPTION:13:00 Registration / Reception\n\nSession 1 Opening\n\n13:20 (O pening remarks) Introduction on the today’s event Prof. Taekwang Jang\, ETH Zurich\, Chair of the IEEE Solid-State Circuits Society\, Switzerland\ n\n13:30 (Welcome address) Ambassador Chang-rok\, Keum Ambassador of the R epublic of Korea to the Swiss Confederation\n\n13:35 (Welcome address) Amb assador Jacque Ducrest Head of International Relations Division\, State Se cretariat for Education\, Research and Innovation\n\nSession 1: Circuit Te chnology (Moderator: Prof. Taekwang Jang)\n\n13:40 Communication Electroni cs\n\n14:00 Imagers Prof. Youngcheol Chae\, Yonsei University\, Korea\n\n1 4:20 Wireless Communication Prof. Hua Wang\, ETH Zürich\, Switzerland\n\n 14:40 Data Converter Circuits Prof. Seung-Tak Ryu\, KAIST\, Korea\n\n15:00 Coffee and networking (Sponsored by IEEE Solid State Circuit Society Swit zerland)\n\nSession 2: Application Technology (Moderator: )\n\n15:20 Weara ble Electronics Prof. Jerald Yoo\, SNU\, Korea\n\n15:40 Brain Machine Inte rface Prof. Mahsa Shoaran\, EPFL\, Switzerland\n\n16:00 Integrated Circuit s for Quantum Computers Prof. Jae-Yoon Sim\, Postech\, Korea\n\n16:20 Chip s for Artificial Intelligence\n\n16:40 Chiplet and high density computing platforms Memory technology for future electronics Silicon fabrication tec hnology beyond Moore’s area\n\n17:00 Closing Remarks and Networking Aper o Dr. Sungsik Lee\, Chair\, Korean Scientists and Engineers Association in Switzerland\n\nRoom: Audi Max HG F30\, Bldg: Hauptgebäude\, Rämistrasse 101\, Zurich\, Switzerland\, Switzerland\, 8006 LOCATION:Room: Audi Max HG F30\, Bldg: Hauptgebäude\, Rämistrasse 101\, Z urich\, Switzerland\, Switzerland\, 8006 ORGANIZER:mathieu.coustans@fhnw.ch SEQUENCE:31 SUMMARY:2024 South Korea and Switzerland Semiconductor Technology Forum URL;VALUE=URI:https://events.vtools.ieee.org/m/421659 X-ALT-DESC:Description: <br /><p style="margin: 0in\; font-family: Calibri\ ; font-size: 11.0pt\;">&nbsp\;</p>\n<p style="margin: 0in\; font-family: C alibri\; font-size: 11.0pt\;">13:00 Registration / Reception</p>\n<p style ="margin: 0in\; font-family: Calibri\; font-size: 11.0pt\;">&nbsp\;</p>\n< p style="margin: 0in\; font-family: Calibri\; font-size: 11.0pt\;">Session 1 Opening&nbsp\;</p>\n<p style="margin: 0in\; font-family: Calibri\; font -size: 11.0pt\;">13:20 (Opening remarks) Introduction on the today&rsquo\; s event Prof. Taekwang Jang\, ETH Zurich\,&nbsp\;Chair of the IEEE Solid-S tate&nbsp\;Circuits Society\, Switzerland</p>\n<p style="margin: 0in\; fon t-family: Calibri\; font-size: 11.0pt\;">13:30 (Welcome address) Ambassado r Chang-rok\, Keum&nbsp\;Ambassador of the Republic of&nbsp\;Korea to the Swiss Confederation</p>\n<p style="margin: 0in\; font-family: Calibri\; fo nt-size: 11.0pt\;">13:35 (Welcome address) Ambassador Jacque Ducrest&nbsp\ ;Head of International Relations&nbsp\;Division\, State Secretariat for&nb sp\;Education\, Research and&nbsp\;Innovation</p>\n<p style="margin: 0in\; font-family: Calibri\; font-size: 11.0pt\;">&nbsp\;</p>\n<p style="margin : 0in\; font-family: Calibri\; font-size: 11.0pt\;">Session 1: Circuit Tec hnology (Moderator: Prof. Taekwang Jang)</p>\n<p style="margin: 0in\; font -family: Calibri\; font-size: 11.0pt\;">13:40 Communication Electronics&nb sp\;</p>\n<p style="margin: 0in\; font-family: Calibri\; font-size: 11.0pt \;">14:00 Imagers Prof. Youngcheol Chae\, Yonsei&nbsp\;University\, Korea< /p>\n<p style="margin: 0in\; font-family: Calibri\; font-size: 11.0pt\;">1 4:20 Wireless Communication Prof. Hua Wang\, ETH Z&uuml\;rich\,&nbsp\;Swit zerland</p>\n<p style="margin: 0in\; font-family: Calibri\; font-size: 11. 0pt\;">14:40 Data Converter Circuits Prof. Seung-Tak Ryu\, KAIST\, Korea</ p>\n<p style="margin: 0in\; font-family: Calibri\; font-size: 11.0pt\;">&n bsp\;</p>\n<p style="margin: 0in\; font-family: Calibri\; font-size: 11.0p t\;">15:00 Coffee and networking (Sponsored by IEEE Solid State Circuit So ciety Switzerland)</p>\n<p style="margin: 0in\; font-family: Calibri\; fon t-size: 11.0pt\;">&nbsp\;</p>\n<p style="margin: 0in\; font-family: Calibr i\; font-size: 11.0pt\;">Session 2: Application Technology (Moderator:&nbs p\; )</p>\n<p style="margin: 0in\; font-family: Calibri\; font-size: 11.0p t\;">15:20 Wearable Electronics Prof. Jerald Yoo\, SNU\, Korea</p>\n<p sty le="margin: 0in\; font-family: Calibri\; font-size: 11.0pt\;">15:40 Brain Machine Interface Prof. Mahsa Shoaran\, EPFL\,&nbsp\;Switzerland</p>\n<p s tyle="margin: 0in\; font-family: Calibri\; font-size: 11.0pt\;">16:00 Inte grated Circuits for Quantum Computers Prof. Jae-Yoon Sim\, Postech\,&nbsp\ ;Korea</p>\n<p style="margin: 0in\; font-family: Calibri\; font-size: 11.0 pt\;">16:20 Chips for Artificial Intelligence&nbsp\;</p>\n<p style="margin : 0in\; font-family: Calibri\; font-size: 11.0pt\;">16:40 Chiplet and high density computing platforms&nbsp\;Memory technology for future electronic s&nbsp\;Silicon fabrication technology beyond Moore&rsquo\;s area</p>\n<p style="margin: 0in\; font-family: Calibri\; font-size: 11.0pt\;">&nbsp\;</ p>\n<p style="margin: 0in\; font-family: Calibri\; font-size: 11.0pt\;">17 :00 Closing Remarks and Networking Apero Dr. Sungsik Lee\, Chair\, Korean& nbsp\;Scientists and Engineers&nbsp\;Association in Switzerland</p> END:VEVENT END:VCALENDAR