BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Warsaw BEGIN:DAYLIGHT DTSTART:20170326T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20161030T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20161130T144235Z UID:03445188-AFF1-11E6-A7C6-0050568D7F66 DTSTART;TZID=Europe/Warsaw:20161208T200000 DTEND;TZID=Europe/Warsaw:20161209T133000 DESCRIPTION:Dean of AGH University's Faculty of Electrical Engineering\, Au tomatics\, Computer Science and Biomedical Engineering together with Depar tment of Measurement and Electronics and IEEE Solid-State Circuit Society Chapter Poland invites for an ADVANCED SHORT COURSE:\n\nAdvanced Short Cou rse on “All-Digital Phase-Locked Loops (ADPLL)”.\n\nProf. Bogdan Stasz ewski (University College Dublin\, Ireland).\n\nThe past several years has seen proliferation of all-digital phase-locked loops (ADPLL) for RF and h igh-performance frequency synthesis due to their clear benefits of flexibi lity\, reconfigurability\, transfer function precision\, settling speed\, frequency modulation capability\, and amenability to integration with digi tal baseband and application processors. When implemented in nanoscale CMO S\, the ADPLL also exhibits advantages of better performance\, lower power consumption\, lower area and cost over the traditional analog-intensive c harge-pump PLL. In a typical ADPLL\, a traditional VCO got directly replac ed by a digitally controlled oscillator (DCO) for generating an output var iable clock\, a traditional phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for detecting phase departu res of the variable clock versus the frequency reference (FREF) clock\, an d an analog loop RC filter got replaced with a digital loop filter. The co nversion gains of the DCO and TDC circuits are readily estimated and compe nsated using ”free” but powerful digital logic.\n\nSpeaker(s): Prof. R obert Bogdan Staszewski\, \, Prof. Robert Bogdan Staszewski\, \n\nAgenda: \nAGH University of Science and Technology\, Building B-1\, room: 121 lect ure hall\n\nDay 1: 8th december 2016:\n\n- All-Digital Phase-Locked Loop ( ADPLL) [3 lectures: 8:00 - 9:30\, 10:00 - 11:30\, 12:00 - 13:30]\n\nDay 2: 9th december 2016:\n\n- Digitally-controlled oscillator (DCO) [2 lectures : 8:00 - 9:30\, 10:00 - 11:30]\n\n- Time-to-digital converter (TDC) [1 lec ture: 12:00 - 13:30]\n\nRecommended Literature: Book: R. B. Staszewski and P. T. Balsara\, All-Digital Frequency Synthesizer in Deep-Submicron CMOS\ , New Jersey: John Wiley & Sons\, Inc.\, Sept. 2006. ISBN: 978-0471772552. \n\nRoom: 121\, Bldg: B-1\, AGH University of Science and Technology\, Av. Mickiewicza 30\, Cracow\, Malopolskie\, Poland\, 30-059 LOCATION:Room: 121\, Bldg: B-1\, AGH University of Science and Technology\, Av. Mickiewicza 30\, Cracow\, Malopolskie\, Poland\, 30-059 ORGANIZER:kasinski@agh.edu.pl SEQUENCE:5 SUMMARY:Advanced Short Course on "All-Digital Phase-Locked Loops (ADPLL)" URL;VALUE=URI:https://events.vtools.ieee.org/m/42283 X-ALT-DESC:Description: <br /><p>Dean of AGH University's Faculty of Electr ical Engineering\, Automatics\, Computer Science and Biomedical Engineerin g together with Department of Measurement and Electronics and IEEE Solid-S tate Circuit Society Chapter Poland invites for an ADVANCED SHORT COURSE:< /p>\n<p>Advanced Short Course on &ldquo\;All-Digital Phase-Locked Loops (A DPLL)&rdquo\;.</p>\n<p>Prof. Bogdan Staszewski (University College Dublin\ , Ireland).</p>\n<p><span lang="EN-US">The past several years has seen pro liferation of all-digital phase-locked loops (ADPLL) for RF and high-perfo rmance frequency synthesis due to their clear benefits of flexibility\, re configurability\, transfer function precision\, settling speed\, frequency modulation capability\, and amenability to integration with digital baseb and and application processors. When implemented in nanoscale CMOS\, the A DPLL also exhibits advantages of better performance\, lower power consumpt ion\, lower area and cost over the traditional analog-intensive charge-pum p PLL. In a typical ADPLL\, a traditional VCO got directly replaced by a d igitally controlled oscillator (DCO) for generating an output variable clo ck\, a traditional phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for detecting phase departures of th e variable clock versus the frequency reference (FREF) clock\, and an anal og loop RC filter got replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits are readily estimated and compensated us ing &rdquo\;free&rdquo\; but powerful digital logic.</span></p><br /><br / >Agenda: <br /><p>AGH University of Science and Technology\, Building B-1\ , room: 121 lecture hall</p>\n<p>Day 1: 8th&nbsp\;december 2016:</p>\n<p>- &nbsp\;All-Digital Phase-Locked Loop (ADPLL) [3 lectures: 8:00 - 9:30\, 10 :00 - 11:30\, 12:00 - 13:30]</p>\n<p>Day 2: 9th december 2016:</p>\n<p>-&n bsp\;Digitally-controlled oscillator (DCO) [2 lectures: 8:00 - 9:30\, 10:0 0 - 11:30]</p>\n<p>-&nbsp\;Time-to-digital converter (TDC) [1 lecture: 12: 00 - 13:30]</p>\n<p>Recommended Literature:&nbsp\;Book: R. B. Staszewski a nd P. T. Balsara\, All-Digital Frequency Synthesizer in Deep-Submicron CMO S\, New Jersey: John Wiley &amp\; Sons\, Inc.\, Sept. 2006. ISBN: 978-0471 772552.</p> END:VEVENT END:VCALENDAR