BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Argentina/Buenos_Aires BEGIN:DAYLIGHT DTSTART:20380119T001407 TZOFFSETFROM:-0300 TZOFFSETTO:-0300 RRULE:FREQ=YEARLY;BYDAY=3TU;BYMONTH=1 TZNAME:-03 END:DAYLIGHT BEGIN:STANDARD DTSTART:20090314T230000 TZOFFSETFROM:-0200 TZOFFSETTO:-0300 RRULE:FREQ=YEARLY;BYDAY=2SA;BYMONTH=3 TZNAME:-03 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20240702T214213Z UID:936F6F8C-F1F2-4D42-B509-7AA1BAB75BF1 DTSTART;TZID=America/Argentina/Buenos_Aires:20240701T160000 DTEND;TZID=America/Argentina/Buenos_Aires:20240701T173000 DESCRIPTION:[Cartel_evento_actualizado_23JUN2024]\nInvitation\n\nIEEE Joint Chapter No. 3 (EDS/SCC) of the Argentina Section invites you to the confe rence "PEfficient Computing for AI and Robotics: From Hardware Accelerator s to Algorithm Design" given by the distinguished SSC IEEE speaker phd. Vi vienne Sze from the Electrical Engineering and Computer Science Department at MIT.\n\nPlease note that the talk is sponsored under the IEEE Electron Devices Society Distinguished Lecturers Program.\n\nAbstract\n\nThe compu te demands of AI and robotics continue to rise due to the rapidly growing volume of data to be processed\; the increasingly complex algorithms for h igher quality of results\; and the demands for energy efficiency and real- time performance. In this talk\, we will discuss the design of efficient h ardware accelerators and the co-design of algorithms and hardware that red uce the energy consumption while delivering real-time and robust performan ce for applications including deep neural networks\, data analytics with s parse tensor algebra\, and autonomous navigation. We will also discuss our recent work that balances flexibility and efficiency for domain-specific accelerators and reduces the cost of analog-to-digital converters for proc essing-in-memory accelerators. Throughout the talk\, we will highlight imp ortant design principles\, methodologies\, and tools that can facilitate a n effective design process.\n\nCo-sponsored by: Universidad Tecnológica N acional Facultad Regional Buenos aires - Departamento de Ingeniería Elect rónica\n\nSpeaker(s): phd. Vivienne Sze\n\nRoom: Departamento de Electró nica\, Universidad Tecnológica Nacional Facultad Regional Buenos Aires\, Medrano 951 \, CABA\, Distrito Federal\, Argentina LOCATION:Room: Departamento de Electrónica\, Universidad Tecnológica Naci onal Facultad Regional Buenos Aires\, Medrano 951 \, CABA\, Distrito Feder al\, Argentina ORGANIZER:eds.sscs.ar@ieee.org SEQUENCE:30 SUMMARY:EDS/SSC DLL - 2024 - Efficient Computing for AI and Robotics: From Hardware Accelerators to Algorithm Design URL;VALUE=URI:https://events.vtools.ieee.org/m/424204 X-ALT-DESC:Description: <br /><p>&nbsp\;</p>\n<table style="border-collapse : collapse\; width: 100%\; border-spacing: 10px\; border: 1px inset rgb(25 5\, 255\, 255)\; margin-right: 0px\; margin-left: auto\;" border="1"><colg roup><col style="width: 58.0488%\;"><col style="width: 42.0488%\;"></colgr oup>\n<tbody>\n<tr>\n<td style="border-width: 1px\; border-color: rgb(255\ , 255\, 255)\; padding: 20px\;"><img style="border-width: 5px\; border-sty le: solid\;" src="https://events.vtools.ieee.org/vtools_ui/media/display/7 a080fc0-c6f1-4751-ba89-29a72c2383df" alt="Cartel_evento_actualizado_23JUN2 024" width="561" height="791"></td>\n<td style="border-width: 1px\; border -color: rgb(255\, 255\, 255)\; padding: 20px\;">\n<h1 style="text-align: l eft\;"><span style="font-weight: 400\;"><span style="font-family: 'arial b lack'\, sans-serif\;">Invitation</span></span></h1>\n<p style="text-align: justify\;">IEEE Joint Chapter No. 3 (EDS/SCC) of the Argentina Section in vites you to the conference "PEfficient Computing for AI and Robotics: Fro m Hardware Accelerators to Algorithm Design" given by the distinguished SS C IEEE speaker phd. Vivienne Sze from the Electrical Engineering and Compu ter Science Department at MIT.</p>\n<p style="text-align: justify\;">Pleas e note that the talk is sponsored under the IEEE Electron Devices Society Distinguished Lecturers Program.</p>\n<p>&nbsp\;</p>\n<p>&nbsp\;</p>\n<h1> <span style="font-family: 'arial black'\, sans-serif\;">Abstract</span></h 1>\n<p style="text-align: justify\;">The compute demands of AI and robotic s continue to rise due to the rapidly growing volume of data to be process ed\; the increasingly complex algorithms for higher quality of results\; a nd the demands for energy efficiency and real-time performance. In this ta lk\, we will discuss the design of efficient hardware accelerators and the co-design of algorithms and hardware that reduce the energy consumption w hile delivering real-time and robust performance for applications includin g deep neural networks\, data analytics with sparse tensor algebra\, and a utonomous navigation.&nbsp\; We will also discuss our recent work that bal ances flexibility and efficiency for domain-specific accelerators and redu ces the cost of analog-to-digital converters for processing-in-memory acce lerators. Throughout the talk\, we will highlight important design princip les\, methodologies\, and tools that can facilitate an effective design pr ocess.</p>\n</td>\n</tr>\n</tbody>\n</table>\n<p><br><br><br></p> END:VEVENT END:VCALENDAR