BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Jerusalem BEGIN:DAYLIGHT DTSTART:20240329T030000 TZOFFSETFROM:+0200 TZOFFSETTO:+0300 RRULE:FREQ=YEARLY;BYDAY=-1FR;BYMONTH=3 TZNAME:IDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20241027T010000 TZOFFSETFROM:+0300 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:IST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20240827T131352Z UID:FC54567D-D2B2-41A1-8DD8-3F03CC072C33 DTSTART;TZID=Asia/Jerusalem:20240826T170000 DTEND;TZID=Asia/Jerusalem:20240826T180000 DESCRIPTION:RE: Monthly webinar – Universal Chiplet Interconnect ExpressT M (UCIeTM): An Open Interconnect Standard for Innovations On-Package\n\nSp eaker: Dr. Debendra Das Sharma\, Senior Fellow\, co-GM Memory and I/O Tech nologies\, Intel\n\nDate: Monday\, August 26th\, 2024 5:00 PM (Israel Time ).\n\nDear IEEE Israel chapter members\, Dear guests\,\n\nThe IEEE Compute r Society Israel conducts a series of webinars in different areas of compu ter systems\, Software engineering\, Computer architectures\, data center\ , accelerators for machine learning\, security\, and more. The webinars of fer insightful and enriching talks held by international leaders and profe ssionals of the computer society sector.\n\nThe next free online webinar w ill include a special talk “Universal Chiplet Interconnect ExpressTM (UC IeTM): An Open Interconnect Standard for Innovations On-Package” by Dr. Debendra Das Sharma\, Senior Fellow\, co-GM Memory and I/O Technologies\, Intel.\n\nA High-performance workloads demand on-package integration of he terogeneous processing units\, on-package memory\, and communication infra structure such as co-packaged optics to meet the demands of the computing landscape. On-package interconnects are a critical component to deliver th e power-efficient performance with the right feature set in this evolving landscape. Universal Chiplet Interconnect Express (UCIe) is an open indust ry standard with a fully specified stack that comprehends plug-and-play in teroperability of chiplets\; like the seamless interoperability on board w ith well-established and successful off-package interconnect standards suc h PCI Express® and Compute Express Link (CXL)®. In this talk\, we will d iscuss the usages and key metrics associated with different technology cho ices in UCIe and how it will evolve going forward from a planar interconne ct (2D/ 2.5D) to 3D to deliver superior power-performance metrics. We will also delve into the challenges and opportunities for chiplets connected t hrough UCIe.\n\nThe Webinar is free\, but pre-registration is required. So \, please sign up using this [link](https://technion.zoom.us/webinar/regis ter/WN_wQ4DQaI5T8mUW_HbIcfDyA#/registration) and the Zoom session details will be provided after registration.\n\nPlease contact us for any further details and updates on the series of IEEE Computer Society Webinars.We are looking forward to your participation and future collaboration.\n\nProf. Avi Mendelson Prof. Freddy Gabbay\nAvi.mendelson@technion.ac.il freddy.gab bay@mail.huji.ac.il\n\nChairman Vice-Chair\n\nVirtual: https://events.vtoo ls.ieee.org/m/430368 LOCATION:Virtual: https://events.vtools.ieee.org/m/430368 ORGANIZER:freddy.gabbay@mail.huji.ac.il SEQUENCE:2 SUMMARY:Webinar - Universal Chiplet Interconnect ExpressTM (UCIeTM): An Ope n Interconnect Standard for Innovations On-Package URL;VALUE=URI:https://events.vtools.ieee.org/m/430368 X-ALT-DESC:Description: <br /><p class="MsoNormal"><span lang="EN-US">RE: M onthly webinar &ndash\; <strong>Universal Chiplet Interconnect Express<sup >TM</sup> (UCIe<sup>TM</sup>): An Open Interconnect Standard for Innovatio ns On-Package</strong></span></p>\n<p class="MsoNormal"><span lang="EN-US" >&nbsp\;</span></p>\n<p class="MsoNormal"><span lang="EN-US">Speaker: </sp an><strong><span lang="EN-US">Dr. Debendra Das Sharma\, Senior Fellow\, co -GM Memory and I/O Technologies\, Intel</span></strong></p>\n<p class="Mso Normal"><strong><span lang="EN-US">&nbsp\;</span></strong></p>\n<p class=" MsoNormal"><span lang="EN-US">Date: </span><strong>Monday\, August 26th\, 2024</strong><strong> <span lang="EN-US">5:00 PM</span> (Israel Time)</str ong><strong><span lang="EN-US">.</span></strong></p>\n<p class="MsoNormal" >&nbsp\;</p>\n<p class="MsoNormal">Dear IEEE Israel chapter members\,&nbsp \;Dear guests\,</p>\n<p class="MsoNormal">The IEEE Computer Society Israel <span lang="EN-US">conducts</span> a series of webinars in different area s of computer systems\, Software engineering\, Computer architectures\, da ta center\, accelerators for machine learning\, security\, and more. The w ebinars offer insightful and enriching talks held by international leaders and professionals of the computer society sector.</p>\n<p class="MsoNorma l">&nbsp\;</p>\n<p class="MsoNormal"><span lang="EN-US">The next</span> fr ee online <span lang="EN-US">webinar will include a special talk &ldquo\;< strong>Universal Chiplet Interconnect Express<sup>TM</sup> (UCIe<sup>TM</s up>): An Open Interconnect Standard for Innovations On-Package</strong>&rd quo\; by <strong>Dr. Debendra Das Sharma\, Senior Fellow\, co-GM Memory an d I/O Technologies\, Intel</strong>.</span></p>\n<p class="MsoNormal"><spa n lang="EN-US">&nbsp\;</span></p>\n<p class="MsoNormal"><span lang="EN-US" >A High-performance workloads demand on-package integration of heterogeneo us processing units\, on-package memory\, and communication infrastructure such as co-packaged optics to meet the demands of the computing landscape . On-package interconnects are a critical component to deliver the power-e fficient performance with the right feature set in this evolving landscape . Universal Chiplet Interconnect Express (UCIe) is an open industry standa rd with a fully specified stack that comprehends plug-and-play interoperab ility of chiplets\; like the seamless interoperability on board with well- established and successful off-package interconnect standards such PCI Exp ress&reg\; and Compute Express Link (CXL)&reg\;. In this talk\, we will di scuss the usages and key metrics associated with different technology choi ces in UCIe and how it will evolve going forward from a planar interconnec t (2D/ 2.5D) to 3D to deliver superior power-performance metrics. We will also delve into the challenges and opportunities for chiplets connected th rough UCIe.</span></p>\n<p class="MsoNormal"><span lang="EN-US">&nbsp\;</s pan></p>\n<p class="MsoNormal"><span lang="EN-US">The Webinar is free\, bu t pre-registration is required. So\, p</span>lease sign up <span lang="EN- US">using this </span><a href="https://technion.zoom.us/webinar/register/W N_wQ4DQaI5T8mUW_HbIcfDyA#/registration"><span lang="EN-US">link</span></a> <span lang="EN-US"> and </span>the Zoom session <span lang="EN-US">details </span>will be provided after registration.</p>\n<p class="MsoNormal"><sp an lang="EN-US">P</span>lease <span lang="EN-US">contact us f</span>or <sp an lang="EN-US">any further</span> details and updates on the series of <s pan lang="EN-US">IEEE Computer Society</span> Webinars<span lang="EN-US">. </span>We are looking forward to your participation and future collaborati on.</p>\n<p class="MsoNormal">&nbsp\;</p>\n<p class="MsoNormal">Prof. Avi Mendelson&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&n bsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\ ;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nb sp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; &nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nb sp\;&nbsp\; Prof. Freddy Gabbay<br><a href="mailto:Avi.mendelson@technion. ac.il">Avi.mendelson@technion.ac.il</a> &nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\ ;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nb sp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; &nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; <a href="m ailto:freddy.gabbay@mail.huji.ac.il"><span lang="EN-US">freddy.gabbay@mail .huji.ac.il</span></a></p>\n<p class="MsoNormal">Chairman&nbsp\;&nbsp\;&nb sp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; &nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbs p\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; &nbsp\; &nbsp\;&nbsp\;&nbsp\ ;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nb sp\;&nbsp\;&nbsp\; Vice-Chair</p> END:VEVENT END:VCALENDAR