BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20240310T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20241103T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20240925T230414Z UID:C57A2B70-D251-4286-860B-5F27AD1AE969 DTSTART;TZID=America/Los_Angeles:20240912T120000 DTEND;TZID=America/Los_Angeles:20240912T130000 DESCRIPTION:[]Thermal management is becoming an ever more critical challeng e for AI chips as the power density increases. Both chip-level and facilit y-level cooling solutions need to be developed and optimized in order to s upport the demand and needs. At the chip level\, advanced packaging techno logies -- such as chiplet architectures and heterogeneous architectures li ke 2.5D\, 3D\, and 3.5D hybrid bonded technologies -- are becoming increas ingly popular for driving performance and cost improvements in AI/ML hardw are. However\, these solutions also introduce additional complexity and th ermal challenges. To address these challenges\, ASIC cooling technology de velopment is a key strategic enabler to ensure the competitiveness and sca lability of AI/ML hardware roadmaps. These technologies aim to solve the h igh total power and increased power density challenges faced by AI/ML syst ems. On the other hand\, at the facility level\, various cold plate design and liquid cooling solutions are developing and need to become more matur e to be deployed in large scale.\nThis presentation identifies areas for f uture thermal technology exploration at both ASIC and facility level that require investment to extend the cooling capabilities of future AI/ML road maps. These areas include:\n• Thermal characterization of on-die thermal models\n• Exploration of thermal interface materials\n• Optimization of cold plate performance\n• Evaluation of future embedded cooling solut ions\n• AALC and liquid cooling solutions at the rack level\nInvesting i n these areas will help ensure the continued development of high-performan ce and scalable AI/ML hardware.\n\nSpeaker(s): Yin Hang\, \n\nAgenda: \nse e ‘Location’ for webex coordinates\n\nVirtual: https://events.vtools.i eee.org/m/430575 LOCATION:Virtual: https://events.vtools.ieee.org/m/430575 ORGANIZER:p.wesling@ieee.org SEQUENCE:26 SUMMARY:Thermal Challenges and Opportunities for AI/ML Hardware: From Chip to Facility URL;VALUE=URI:https://events.vtools.ieee.org/m/430575 X-ALT-DESC:Description: <br /><p><img style="float: right\;" src="https://e vents.vtools.ieee.org/vtools_ui/media/display/e1506c09-e94e-4d9f-ab44-ad70 919b9da9" alt="" width="500" height="250">Thermal management is becoming a n ever more critical challenge for AI chips as the power density increases . Both chip-level and facility-level cooling solutions need to be develope d and optimized in order to support the demand and needs. At the chip leve l\, advanced packaging technologies -- such as chiplet architectures and h eterogeneous architectures like 2.5D\, 3D\, and 3.5D hybrid bonded technol ogies -- are becoming increasingly popular for driving performance and cos t improvements in AI/ML hardware. However\, these solutions also introduce additional complexity and thermal challenges. To address these challenges \, ASIC cooling technology development is a key strategic enabler to ensur e the competitiveness and scalability of AI/ML hardware roadmaps. These te chnologies aim to solve the high total power and increased power density c hallenges faced by AI/ML systems. On the other hand\, at the facility leve l\, various cold plate design and liquid cooling solutions are developing and need to become more mature to be deployed in large scale.<br>&nbsp\;Th is presentation identifies areas for future thermal technology exploration at both ASIC and facility level that require investment to extend the coo ling capabilities of future AI/ML roadmaps. These areas include:<br>&bull\ ; &nbsp\; &nbsp\;Thermal characterization of on-die thermal models<br>&bul l\; &nbsp\; &nbsp\;Exploration of thermal interface materials<br>&bull\; & nbsp\; &nbsp\;Optimization of cold plate performance<br>&bull\; &nbsp\; &n bsp\;Evaluation of future embedded cooling solutions<br>&bull\; &nbsp\; &n bsp\;AALC and liquid cooling solutions at the rack level<br>&nbsp\;Investi ng in these areas will help ensure the continued development of high-perfo rmance and scalable AI/ML hardware.</p><br /><br />Agenda: <br /><p>see &l squo\;Location&rsquo\; for webex coordinates</p> END:VEVENT END:VCALENDAR