BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:US/Pacific
BEGIN:DAYLIGHT
DTSTART:20160313T030000
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3
TZNAME:PDT
END:DAYLIGHT
BEGIN:STANDARD
DTSTART:20161106T010000
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11
TZNAME:PST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20170121T224007Z
UID:64AB2FEA-E02A-11E6-A7C6-0050568D7F66
DTSTART;TZID=US/Pacific:20161103T180000
DTEND;TZID=US/Pacific:20161103T200000
DESCRIPTION:Abstract:\n\nPotential challenges with managing mechanical stre
 ss and the consequent effects on device performance for advanced three-dim
 ensional (3-D) IC technologies are outlined. The growing need in a simulat
 ion-based design verification flow capable of analyzing and detecting acro
 ss-die out-of-spec stress-induced variations in MOSFET/FinFET electrical c
 haracteristics is addressed. A physics-based compact modeling methodology 
 for multi-scale simulation of all contributing components of stress induce
 d variability is described. A simulation flow that provides an interface b
 etween layout formats (GDS II\, OASIS)\, and FEA-based package-scale tools
 \, is developed. The EDA tool-prototype\, developed on the basis of propos
 ed methodology\, can be used to optimize the floorplan for different circu
 its and packaging technologies\, and/or for the final design signoff\, for
  all stress induced phenomena. A calibration technique based on fitting to
  measured electrical characterization data is presented\, along with corre
 lation of the electrical characteristics to direct physical strain measure
 ments. The limited characterization or measurement capabilities for 3-D IC
  stacks and a strict “good die” requirement make this type of analysis
  critical in order to achieve an acceptable level of functional and parame
 tric yield.\n\nFood sponsored by: ICE Labs\, ISO 9001 & 17025 Reliability 
 Test Lab. [www.icenginc.com](http://www.icenginc.com/)\n\nSpeaker(s): Vale
 riy Sukharev\, \, Valeriy Sukharev\, \n\nAgenda: \nCheck in and food at 6:
 00PM - 6:30 PM. Presentation from 6:30 PM to 7:30 PM.\n\nRoom: Building-B 
 Cafeteria\, Bldg: Qualcomm\, Inc. \, 3165 Kifer Road\, Santa Clara\, Calif
 ornia\, United States\, 95051
LOCATION:Room: Building-B Cafeteria\, Bldg: Qualcomm\, Inc. \, 3165 Kifer R
 oad\, Santa Clara\, California\, United States\, 95051
ORGANIZER:yun.ann.12@gmail.com
SEQUENCE:1
SUMMARY:CPI stress induced carrier mobility shift in advanced silicon nodes
URL;VALUE=URI:https://events.vtools.ieee.org/m/43313
X-ALT-DESC:Description: <br /><div>\n<div>\n<p><strong>Abstract</strong>:&n
 bsp\;</p>\n</div>\n</div>\n<div>\n<p class="p1"><span id="docs-internal-gu
 id-7c854653-df20-51b1-0649-e833780b46dd">Potential challenges with managin
 g mechanical stress and the consequent effects on device performance for a
 dvanced three-dimensional (3-D) IC technologies are outlined. The growing 
 need in a simulation-based design verification flow capable of analyzing a
 nd detecting across-die out-of-spec stress-induced variations in MOSFET/Fi
 nFET electrical characteristics is addressed. A physics-based compact mode
 ling methodology for multi-scale simulation of all contributing components
  of stress induced variability is described. A simulation flow that provid
 es an interface between layout formats (GDS II\, OASIS)\, and FEA-based pa
 ckage-scale tools\, is developed. The EDA tool-prototype\, developed on th
 e basis of proposed methodology\, can be used to optimize the floorplan fo
 r different circuits and packaging technologies\, and/or for the final des
 ign signoff\, for all stress induced phenomena. A calibration technique ba
 sed on fitting to measured electrical characterization data is presented\,
  along with correlation of the electrical characteristics to direct physic
 al strain measurements. The limited characterization or measurement capabi
 lities for 3-D IC stacks and a strict &ldquo\;good die&rdquo\; requirement
  make this type of analysis critical in order to achieve an acceptable lev
 el of functional and parametric yield.</span></p>\n<div>\n<div>\n<p><stron
 g>Food sponsored by:</strong>&nbsp\;ICE Labs\, ISO 9001 &amp\; 17025 Relia
 bility&nbsp\;Test Lab.&nbsp\;<strong><a href="http://www.icenginc.com/" re
 l="nofollow">www.icenginc.com</a></strong></p>\n</div>\n</div>\n</div><br 
 /><br />Agenda: <br /><p>Check in and food at 6:00PM - 6:30 PM. Presentati
 on from 6:30 PM to 7:30 PM.</p>
END:VEVENT
END:VCALENDAR