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DTSTAMP:20240918T061548Z
UID:FB9DBBF2-58BF-4915-8821-F79B6D249520
DTSTART;TZID=Europe/Paris:20240917T110000
DTEND;TZID=Europe/Paris:20240917T140000
DESCRIPTION:The size and complexity of recent deep learning models continue
  to increase exponentially\, causing a serious amount of hardware overhead
 s for training those models. Contrary to inference-only hardware\, neural 
 network training is very sensitive to computation errors\; hence\, trainin
 g processors must support high-precision computation to avoid a large perf
 ormance drop\, severely limiting their processing efficiency. This talk wi
 ll introduce a comprehensive design approach to arrive at an optimal train
 ing processor design. More specifically\, the talk will discuss how we sho
 uld make important design decisions for training processors in more depth\
 , including i) hardware-friendly training algorithms\, ii) optimal data fo
 rmats\, and iii) processor architecture for high precision and utilization
 .\n\nRoom: Amphithéâtre Denis Papin\, INSA Centre Val de Loire\, 3 Rue d
 e la Chocolaterie\, Blois\, Centre\, France\, 41034
LOCATION:Room: Amphithéâtre Denis Papin\, INSA Centre Val de Loire\, 3 Ru
 e de la Chocolaterie\, Blois\, Centre\, France\, 41034
ORGANIZER:
SEQUENCE:12
SUMMARY:DL : Designing an optimal hardware solution for deep neural network
  training
URL;VALUE=URI:https://events.vtools.ieee.org/m/433172
X-ALT-DESC:Description: <br /><p class="MsoNormal"><span lang="EN-US" style
 ="mso-ansi-language: EN-US\;">The size and complexity of recent deep learn
 ing models continue to increase exponentially\, causing a serious amount o
 f hardware overheads for training those models. Contrary to inference-only
  hardware\, neural network training is very sensitive to computation error
 s\; hence\, training processors must support high-precision computation to
  avoid a large performance drop\, severely limiting their processing effic
 iency. This talk will introduce a comprehensive design approach to arrive 
 at an optimal training processor design. More specifically\, the talk will
  discuss how we should make important design decisions for training proces
 sors in more depth\, including i) hardware-friendly training algorithms\,&
 nbsp\;ii) optimal data formats\, and&nbsp\;iii) processor architecture for
  high precision and utilization.</span></p>
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