BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Warsaw BEGIN:DAYLIGHT DTSTART:20240331T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20241027T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20241022T074704Z UID:9D6F5578-EC4A-41AB-B609-94301AE297C2 DTSTART;TZID=Europe/Warsaw:20241021T133000 DTEND;TZID=Europe/Warsaw:20241021T153000 DESCRIPTION:Place Holder (exact hours and lecture hall to be specified late r) 13:00 - 18:00 CEST.\n\nPlace: AGH University of Kraków\, Av. Mickiewic za 30 B1\, Kraków\, Poland\n\nType of meeting: Hybrid - On-site and remot e.\n\nDigitally-Enhanced Clock Generation and Distribution\n\nAdvancements in technology scaling have ushered in larger systems boasting enhanced fu nctionality\, increased operational speed\, and expanded data bandwidth. H owever\, these benefits come with more demanding clocking requirements\, i ncluding extended distribution distances and heightened timing precision. Furthermore\, technology scaling has rendered traditional analog design ch allenging. Wider PVT variations necessitate intensive calibration efforts\ , and increased integration levels call for resilience against external no ise sources. Moreover\, the fact that reference frequency and loop bandwid th do not scale at the same rate as technology leads to prohibitive costs for oversized loop filters. While pure analog implementations offer intuit ive operation and elegant analysis\, clocking circuits incorporating digit al elements offer effective solutions to these challenges.\n\nThis present ation will cover how digital circuits can enhance clock generation and dis tribution through techniques like calibration and signal processing. Begin ning with well-established methods that harness the mixed-signal nature of PLLs\, such as delta-sigma modulation for the MDD in fractional-N PLLs\, the presentation will shift toward digital-intensive architectures. It wil l focus on techniques that leverage digital implementations for error dete ction and enhance timing accuracy through either analog or digital correct ion. State-of-the-art designs featuring runtime calibration and power nois e cancellation for clock generation and distribution will also be introduc ed. This talk will conclude with insights into future challenges and trend s.\n\nCo-sponsored by: Silicon Creations\n\nSpeaker(s): Ping-Hsuan Hsieh ( Tsing Hua University\, Hsinchu\, Taiwan\, \n\nBldg: B1 \, AGH University o f Krakow\, Krakow\, Malopolskie\, Poland\, 30-059 LOCATION:Bldg: B1 \, AGH University of Krakow\, Krakow\, Malopolskie\, Pola nd\, 30-059 ORGANIZER:krzysztof.kasinski@siliconcr.com SEQUENCE:6 SUMMARY:Ping-Hsuan Hsieh - Digitally-Enhanced Clock Generation and Distribu tion (IEEE SSCS Chapter Poland) URL;VALUE=URI:https://events.vtools.ieee.org/m/434198 X-ALT-DESC:Description: <br /><p>Place Holder (exact hours and lecture hall to be specified later) 13:00 - 18:00 CEST.</p>\n<p>Place: AGH University of Krak&oacute\;w\, Av. Mickiewicza 30 B1\, Krak&oacute\;w\, Poland</p>\n< p>Type of meeting: Hybrid - On-site and remote.</p>\n<p>&nbsp\;</p>\n<p><s trong>Digitally-Enhanced Clock Generation and Distribution</strong></p>\n< p>Advancements in technology scaling have ushered in larger systems boasti ng enhanced functionality\, increased operational speed\, and expanded dat a bandwidth. However\, these benefits come with more demanding clocking re quirements\, including extended distribution distances and heightened timi ng precision. Furthermore\, technology scaling has rendered traditional an alog design challenging. Wider PVT variations necessitate intensive calibr ation efforts\, and increased integration levels call for resilience again st external noise sources. Moreover\, the fact that reference frequency an d loop bandwidth do not scale at the same rate as technology leads to proh ibitive costs for oversized loop filters. While pure analog implementation s offer intuitive operation and elegant analysis\, clocking circuits incor porating digital elements offer effective solutions to these challenges.</ p>\n<p>This presentation will cover how digital circuits can enhance clock generation and distribution through techniques like calibration and signa l processing. Beginning with well-established methods that harness the mix ed-signal nature of PLLs\, such as delta-sigma modulation for the MDD in f ractional-N PLLs\, the presentation will shift toward digital-intensive ar chitectures. It will focus on techniques that leverage digital implementat ions for error detection and enhance timing accuracy through either analog or digital correction. State-of-the-art designs featuring runtime calibra tion and power noise cancellation for clock generation and distribution wi ll also be introduced. This talk will conclude with insights into future c hallenges and trends.</p> END:VEVENT END:VCALENDAR