BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Warsaw BEGIN:DAYLIGHT DTSTART:20240331T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20241027T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20241022T073511Z UID:E5EF0B67-A436-446D-87CC-E7A8D3FE896A DTSTART;TZID=Europe/Warsaw:20241010T133000 DTEND;TZID=Europe/Warsaw:20241010T180000 DESCRIPTION:Digital equalization for Multilevel signaling in high-speed Ser Des\n\nMultilevel signaling has extended the lifeline of wireline signalin g beyond 100 Gb/s. But it’s SNR penalty has mandated much more sophistic ated equalization that is more suitable for digital implementation. This p resentation aims at bridging the gap between well-understood analog/mixed- signal solutions and today’s DSP-based solutions. Starting from traditio nal analog architectures\, this talk will walk through the evolution towar d today’s DSP-based equalization and provide the background for tomorrow ’s sequence decoding.\n\nEvolution of the Timing Recovery techniques in High-speed Links\n\nTiming recovery techniques have evolved significantly over the last 25 years of high-speed link design. In the first decade\, th is evolution was motivated by technology scaling and scalability\, where i t gradually moved to a fully digital implementation from an analog PLL-bas ed approach. However\, the evolution in the last decade is motivated by th e adoption of multilevel signaling. The emergence of MMSE as an alternativ e to 2X oversampled solutions is an example of such recent developments. T his talk aims to bring designers up to speed on the state-of-the-art ADC-D SP solutions\, explain their motivation\, and finally conclude with silico n results to validate the performance improvement achievable in these arch itectures.\n\nLow-jitter flexible frequency generation for next-generation communication systems\n\nThe next-generation wireline and wireless system s promise wider bandwidth to enable a vast range of applications\, includi ng autonomous vehicles\, virtual reality\, and the internet of things. Suc h high data rates mandate precise clock generation to meet the timing budg et. At the same time\, flexibility to support multiple standards and scala bility to meet higher integration density introduces additional dimensions to the clocking challenge. This talk will discuss recent circuit and arch itecture innovations to address these challenges. Starting from simple pha se-locking concepts such as PLL\, DLL and ILO\, this talk will explain how the combination of these techniques is adopted in modern communication sy stems. It will also describe two example cases - i. A 28 GHz frequency syn thesizer for 5G LO based beam forming\, and ii. A flexible clocking soluti on for 10Gb/s to 112 Gb/s SerDes in 7 nm finFET technology.\n\nCo-sponsore d by: Silicon Creations\n\nSpeaker(s): Masum Hossain (Carleton University\ , Ottawa)\, \n\nRoom: 307/308\, Bldg: C-6 (Centrum Energetyki)\, AGH Unive rsity of Kraków\, Av. Mickiewicza 30\, Krakow\, Malopolskie\, Poland\, 30 -059 LOCATION:Room: 307/308\, Bldg: C-6 (Centrum Energetyki)\, AGH University of Kraków\, Av. Mickiewicza 30\, Krakow\, Malopolskie\, Poland\, 30-059 ORGANIZER:krzysztof.kasinski@siliconcr.com SEQUENCE:8 SUMMARY:Masum Hossain - Short Course on High-Speed Interfaces (IEEE SSCS Ch apter Poland) URL;VALUE=URI:https://events.vtools.ieee.org/m/434201 X-ALT-DESC:Description: <br /><h3><strong>Digital equalization for Multilev el signaling in high-speed SerDes</strong></h3>\n<p>Multilevel signaling h as extended the lifeline of wireline signaling beyond 100 Gb/s. But it&rsq uo\;s SNR penalty has mandated much more sophisticated equalization that i s more suitable for digital implementation. This presentation aims at brid ging the gap between well-understood analog/mixed-signal solutions and tod ay&rsquo\;s DSP-based solutions. Starting from traditional analog architec tures\, this talk will walk through the evolution toward today&rsquo\;s DS P-based equalization and provide the background for tomorrow&rsquo\;s sequ ence decoding.</p>\n<p>&nbsp\;</p>\n<h3><strong>Evolution of the Timing Re covery techniques in High-speed Links</strong></h3>\n<p>Timing recovery te chniques have evolved significantly over the last 25 years of high-speed l ink design. In the first decade\, this evolution was motivated by technolo gy scaling and scalability\, where it gradually moved to a fully digital i mplementation from an analog PLL-based approach. However\, the evolution i n the last decade is motivated by the adoption of multilevel signaling. Th e emergence of MMSE as an alternative to 2X oversampled solutions is an ex ample of such recent developments. This talk aims to bring designers up to speed on the state-of-the-art ADC-DSP solutions\, explain their motivatio n\, and finally conclude with silicon results to validate the performance improvement achievable in these architectures.</p>\n<p>&nbsp\;</p>\n<h3><s trong>Low-jitter flexible frequency generation for next-generation communi cation systems</strong></h3>\n<p>The next-generation wireline and wireless systems promise wider bandwidth to enable a vast range of applications\, including autonomous vehicles\, virtual reality\, and the internet of thin gs. Such high data rates mandate precise clock generation to meet the timi ng budget. At the same time\, flexibility to support multiple standards an d scalability to meet higher integration density introduces additional dim ensions to the clocking challenge. This talk will discuss recent circuit a nd architecture innovations to address these challenges. Starting from sim ple phase-locking concepts such as PLL\, DLL and ILO\, this talk will expl ain how the combination of these techniques is adopted in modern communica tion systems. It will also describe two example cases - i. A 28 GHz freque ncy synthesizer for 5G LO based beam forming\, and ii. A flexible clocking solution for 10Gb/s to 112 Gb/s SerDes in 7 nm finFET technology.</p>\n<p >&nbsp\;</p> END:VEVENT END:VCALENDAR