BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20240310T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20241103T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20241014T130110Z UID:F5278114-50A4-4BE7-9AB6-82E6D2E7404C DTSTART;TZID=America/New_York:20241007T110000 DTEND;TZID=America/New_York:20241007T130000 DESCRIPTION:Silicon photonics are the semiconductor integration of EIC and PIC on a silicon substrate (wafer) with complementary metal-oxide semicond uctor (CMOS) technology. On the other hand\, co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate the optical engin e (OE) which consists of photonic ICs (PIC) and the electrical engine (EE) which consists of the electronic ICs (EIC) as well as the switch ASIC (ap plication specific IC). The advantages of CPO are: (a) to reduce the lengt h of the electrical interface between the OE/EE (or PIC/EIC) and the ASIC\ , (b) to reduce the energy required to drive the signal\, and (c) to cut t he latency which leads to better electrical performance. In the next few y ears\, we will see more implementations of a higher level of heterogeneous integration of PIC and EIC\, whether it is for performance\, form factor\ , power consumption or cost.\n\nSpeaker(s): John H Lau\, \n\nAgenda: \nThe content of this lecture is shown below.\n\n-\nSilicon Photonics\n\n-\nDat a Centers\n\n-\nOptical Transceivers\n\n-\nOptical Engine (OE) and Electri cal Engine (EE)\n\n-\nOBO (on-board optics)\n\n-\nNPO (near-board optics)\ n\n-\nCPO (co-packaged optics)\n\n-\nIntegration of the PIC and EIC\n\n-\n 2D Heterogeneous Integration of PIC and EIC\n\n-\n2D Heterogeneous Integra tion of ASIC Switch\, PIC and EIC\n\n-\n2D Heterogeneous Integration of AS IC Switch\, PIC and EIC with Bridges\n\n-\n3D Heterogeneous Integration of PIC and EIC\n\n-\n3D Heterogeneous Integration of ASIC Switch\, PIC and E IC\n\n-\n3D Heterogeneous Integration of ASIC Switch\, PIC and EIC with Br idges\n\n-\nHeterogeneous Integration of ASIC Switch\, PIC and EIC on Glas s Substrate\n\n-\nSummary\n\nRoom: HA 401\, Bldg: Haultain Building\, 170 College St\, Toronto\, Ontario\, Canada\, M5S 3E3\, Virtual: https://event s.vtools.ieee.org/m/436266 LOCATION:Room: HA 401\, Bldg: Haultain Building\, 170 College St\, Toronto\ , Ontario\, Canada\, M5S 3E3\, Virtual: https://events.vtools.ieee.org/m/4 36266 ORGANIZER: SEQUENCE:20 SUMMARY:Co-Packaged Optics - Heterogeneous Integration of Photonic IC and E lectronic IC URL;VALUE=URI:https://events.vtools.ieee.org/m/436266 X-ALT-DESC:Description: <br /><p dir="ltr">Silicon photonics are the semico nductor integration of EIC and PIC on a silicon substrate (wafer) with com plementary metal-oxide semiconductor (CMOS) technology. On the other hand\ , co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate the optical engine (OE) which consists of photonic ICs (PIC) and the electrical engine (EE) which consists of the electronic ICs (EIC) as well as the switch ASIC (application specific IC). The advantages of C PO are: (a) to reduce the length of the electrical interface between the O E/EE (or PIC/EIC) and the ASIC\, (b) to reduce the energy required to driv e the signal\, and (c) to cut the latency which leads to better electrical performance. In the next few years\, we will see more implementations of a higher level of heterogeneous integration of PIC and EIC\, whether it is for performance\, form factor\, power consumption or cost.</p><br /><br / >Agenda: <br /><p dir="ltr">The content of this lecture is shown below.</p >\n<ul>\n<li dir="ltr" aria-level="1">\n<p dir="ltr" role="presentation">S ilicon Photonics</p>\n</li>\n<li dir="ltr" aria-level="1">\n<p dir="ltr" r ole="presentation">Data Centers</p>\n</li>\n<li dir="ltr" aria-level="1">\ n<p dir="ltr" role="presentation">Optical Transceivers</p>\n</li>\n<li dir ="ltr" aria-level="1">\n<p dir="ltr" role="presentation">Optical Engine (O E) and Electrical Engine (EE)</p>\n</li>\n<li dir="ltr" aria-level="1">\n< p dir="ltr" role="presentation">OBO (on-board optics)</p>\n</li>\n<li dir= "ltr" aria-level="1">\n<p dir="ltr" role="presentation">NPO (near-board op tics)</p>\n</li>\n<li dir="ltr" aria-level="1">\n<p dir="ltr" role="presen tation">CPO (co-packaged optics)</p>\n</li>\n<li dir="ltr" aria-level="1"> \n<p dir="ltr" role="presentation">Integration of the PIC and EIC</p>\n</l i>\n<li dir="ltr" aria-level="1">\n<p dir="ltr" role="presentation">2D Het erogeneous Integration of PIC and EIC</p>\n</li>\n<li dir="ltr" aria-level ="1">\n<p dir="ltr" role="presentation">2D Heterogeneous Integration of AS IC Switch\, PIC and EIC</p>\n</li>\n<li dir="ltr" aria-level="1">\n<p dir= "ltr" role="presentation">2D Heterogeneous Integration of ASIC Switch\, PI C and EIC with Bridges</p>\n</li>\n<li dir="ltr" aria-level="1">\n<p dir=" ltr" role="presentation">3D Heterogeneous Integration of PIC and EIC</p>\n </li>\n<li dir="ltr" aria-level="1">\n<p dir="ltr" role="presentation">3D Heterogeneous Integration of ASIC Switch\, PIC and EIC</p>\n</li>\n<li dir ="ltr" aria-level="1">\n<p dir="ltr" role="presentation">3D Heterogeneous Integration of ASIC Switch\, PIC and EIC with Bridges</p>\n</li>\n<li dir= "ltr" aria-level="1">\n<p dir="ltr" role="presentation">Heterogeneous Inte gration of ASIC Switch\, PIC and EIC on Glass Substrate</p>\n</li>\n<li di r="ltr" aria-level="1">\n<p dir="ltr" role="presentation">Summary</p>\n</l i>\n</ul>\n<p>&nbsp\;</p> END:VEVENT END:VCALENDAR