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DTSTART:20241027T020000
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DTSTAMP:20241101T071611Z
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DTSTART;TZID=Europe/Berlin:20241031T143000
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DESCRIPTION:Memory technology is not only the pillar of the present semicon
 ductor industry\, but it also plays a critical role in various innovation 
 forefronts of future\, such as big data storage/processing\, AI accelerati
 on\, neuromorphic computing\, hardware security\, combinatorial optimizer\
 , etc. Memory-centric architectures and computing systems promise to provi
 de unprecedented parallelism\, energy efficiency\, and density beyond the 
 conventional von Neumann architectures. In this intelligent memory era\, b
 reakthroughs in the memory device\, circuit\, and architecture are require
 d. We will talk about the latest ferroelectric and magnetic memory develop
 ment in NYCU\, including BEOL-compatible ferroelectric transistors\, ferro
 electric tunnel junctions\, and compact STT-MRAM neuron devices. Demonstra
 tions of high energy-efficiency in-memory computing and in-memory annealin
 g will also be highlighted\, and the challenges and potential solutions in
  computing precision\, device/circuit variation\, and area/energy efficien
 cy will be addressed. Our approach is showcased using a recent SRAM-based 
 in-memory computing macro achieving unprecedentedly high energy efficiency
  of 20943 TOPS/W.\n\nSpeaker(s): Alex\, \n\nRoom: 80\, Bldg: Faculty of El
 ectrical Engineering\, Czech Technical University in Prague\, Technicka 2\
 , Prague\, Czech Republic\, Czech Republic\, 16627\, Virtual: https://even
 ts.vtools.ieee.org/m/437147
LOCATION:Room: 80\, Bldg: Faculty of Electrical Engineering\, Czech Technic
 al University in Prague\, Technicka 2\, Prague\, Czech Republic\, Czech Re
 public\, 16627\, Virtual: https://events.vtools.ieee.org/m/437147
ORGANIZER:hazdrap@fel.cvut.cz
SEQUENCE:66
SUMMARY:Intelligent Memory in Future High-Performance Computing
URL;VALUE=URI:https://events.vtools.ieee.org/m/437147
X-ALT-DESC:Description: <br /><p>Memory technology is not only the pillar o
 f the present semiconductor industry\, but it also plays a critical role i
 n various innovation forefronts of future\, such as big data storage/proce
 ssing\, AI acceleration\, neuromorphic computing\, hardware security\, com
 binatorial optimizer\, etc. Memory-centric architectures and computing sys
 tems promise to provide unprecedented parallelism\, energy efficiency\, an
 d density beyond the conventional von Neumann architectures. In this intel
 ligent memory era\, breakthroughs in the memory device\, circuit\, and arc
 hitecture are required. We will talk about the latest ferroelectric and ma
 gnetic memory development in NYCU\, including BEOL-compatible ferroelectri
 c transistors\, ferroelectric tunnel junctions\, and compact STT-MRAM neur
 on devices. Demonstrations of high energy-efficiency in-memory computing a
 nd in-memory annealing will also be highlighted\, and the challenges and p
 otential solutions in computing precision\, device/circuit variation\, and
  area/energy efficiency will be addressed. Our approach is showcased using
  a recent SRAM-based in-memory computing macro achieving unprecedentedly h
 igh energy efficiency of 20943 TOPS/W.</p>
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