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DTSTART:20240310T030000
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DTSTAMP:20241106T010259Z
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DTSTART;TZID=America/New_York:20241101T120000
DTEND;TZID=America/New_York:20241101T130000
DESCRIPTION:Abstract: While silicon scaling has reached astonishing levels 
 over the last half century\, there has not been a corresponding level of s
 caling in electronic packaging technology. However\, Artificial Intelligen
 ce (AI) architectures are now changing the landscape\, increasingly moving
  us towards advanced packaging technology and Heterogeneous Integration (H
 I). What are these unique requirements of AI which are driving the need fo
 r HI? What are some of the unique challenges in semiconductor and packagin
 g technologies that must be overcome to make this successful? This seminar
  will discuss key HI methods including interposers\, fan out wafer level p
 rocessing\, silicon bridges\, and 3D integration to see how they can be le
 veraged to achieve AI architectures.\n\n[]\n\nSpeaker(s): Dr. Mukta Farooq
 \, \n\nVirtual: https://events.vtools.ieee.org/m/440607
LOCATION:Virtual: https://events.vtools.ieee.org/m/440607
ORGANIZER:manohar.bongarala@nokia-bell-labs.com
SEQUENCE:15
SUMMARY:Heterogeneous Integration for AI Architectures 
URL;VALUE=URI:https://events.vtools.ieee.org/m/440607
X-ALT-DESC:Description: <br /><p style="text-align: left\;"><span style="fo
 nt-family: arial\, helvetica\, sans-serif\; font-size: 14pt\;"><strong>Abs
 tract: </strong>While silicon scaling has reached astonishing levels over 
 the last half century\, there has not been a corresponding level of scalin
 g in electronic packaging technology. However\, Artificial Intelligence (A
 I) architectures are now changing the landscape\, increasingly moving us t
 owards advanced packaging technology and Heterogeneous Integration (HI). W
 hat are these unique requirements of AI which are driving the need for HI?
  What are some of the unique challenges in semiconductor and packaging tec
 hnologies that must be overcome to make this successful? This seminar will
  discuss key HI methods including interposers\, fan out wafer level proces
 sing\, silicon bridges\, and 3D integration to see how they can be leverag
 ed to achieve AI architectures.</span></p>\n<p style="text-align: left\;">
 <img src="https://events.vtools.ieee.org/vtools_ui/media/display/a88f35e8-
 29b2-4306-8b2a-eac4eed33c24" alt="" width="500" height="250"></p>\n<p>&nbs
 p\;</p>
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