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DESCRIPTION:ABSTRACT\nAggressively scaled transistor technologies with meta
 l gate/high-k stacks encounter additional reliability challenges beside bi
 as temperature instability (BTI) in PMOS and NMOS devices\, time-dependent
  dielectric breakdown and hot carrier degradation. Time-zero variability a
 nd variability induced by device aging is a growing concern which needs to
  be modeled using stochastic processes. The physical nature of the stochas
 tic process remains under debate and to support model development efforts 
 large statistical data sets are essential. In addition\, self- heating dur
 ing reliability testing can be observed in novel device structures like bu
 lk FinFET\, SOI FinFETs\, FDSOI and gate-all-around devices and needs prop
 er attention. Furthermore\, to increase the confidence in the discrete dev
 ice reliability models\, device-to-circuit correlations need to be establi
 shed. In this presentation we discuss how to obtain stochastic BTI data fo
 r discrete SRAM and logic devices beyond 3 sigmas\, address device-to-circ
 uit correlations using ring- oscillators and explore self-heating effects 
 in FinFET and SOI devices.\n\nSpeaker(s): Dr. Andreas Kerber\, \n\nBldg: Q
 ualcomm Q Auditorium\, 6455 Lusk Blvd\,\, San Diego\, California\, United 
 States\, Virtual: https://events.vtools.ieee.org/m/444640
LOCATION:Bldg: Qualcomm Q Auditorium\, 6455 Lusk Blvd\,\, San Diego\, Calif
 ornia\, United States\, Virtual: https://events.vtools.ieee.org/m/444640
ORGANIZER:jfshi@ieee.org
SEQUENCE:104
SUMMARY:Reliability of Metal Gate / High-K CMOS devices
URL;VALUE=URI:https://events.vtools.ieee.org/m/444640
X-ALT-DESC:Description: <br /><p>ABSTRACT<br>Aggressively scaled transistor
  technologies with metal gate/high-k stacks encounter additional reliabili
 ty challenges beside bias temperature instability (BTI) in PMOS and NMOS d
 evices\, time-dependent dielectric breakdown and hot carrier degradation. 
 Time-zero variability and variability induced by device aging is a growing
  concern which needs to be modeled using stochastic processes. The physica
 l nature of the stochastic process remains under debate and to support mod
 el development efforts large statistical data sets are essential. In addit
 ion\, self- heating during reliability testing can be observed in novel de
 vice structures like bulk FinFET\, SOI FinFETs\, FDSOI and gate-all-around
  devices and needs proper attention. Furthermore\, to increase the confide
 nce in the discrete device reliability models\, device-to-circuit correlat
 ions need to be established. In this presentation we discuss how to obtain
  stochastic BTI data for discrete SRAM and logic devices beyond 3 sigmas\,
  address device-to-circuit correlations using ring- oscillators and explor
 e self-heating effects in FinFET and SOI devices.</p>
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