BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Warsaw BEGIN:DAYLIGHT DTSTART:20250330T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20241027T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250304T093850Z UID:D992C238-1513-40A3-ABAF-6818DDE6636A DTSTART;TZID=Europe/Warsaw:20241202T110000 DTEND;TZID=Europe/Warsaw:20241202T123000 DESCRIPTION:Introduction to “All-Digital Phase-Locked Loops (ADPLL)” - Bogdan Staszewski - SSCS Chapter Poland Seminar\n\nAGH University of Krak ów\, Lecture hall H-24\, building B-1.\n\nThe past two decades has seen p roliferation of all-digital phase-locked loops (ADPLL) for RF and high-per formance frequency synthesis due to their clear benefits of flexibility\, reconfigurability\, transfer function precision\, settling speed\, frequen cy modulation capability\, and amenability to integration with digital bas eband and application processors. When implemented in nanoscale CMOS\, the ADPLL also exhibits advantages of better performance\, lower power consum ption\, lower area and cost over the traditional analog-intensive charge-p ump PLL. In a typical ADPLL\, a traditional VCO got directly replaced by a digitally controlled oscillator (DCO) for generating an output variable c lock\, a traditional phase/frequency detector and a charge pump got replac ed by a time-to-digital converter (TDC) for detecting phase departures of the variable clock versus the frequency reference (FREF) clock\, and an an alog loop RC filter got replaced with a digital loop filter. The conversio n gains of the DCO and TDC circuits are readily estimated and compensated using “free” but powerful digital logic.\n\nCo-sponsored by: Silicon C reations\n\nRoom: H24\, Bldg: B1\, AGH University of Krakow\, Av. Mickiewi cza 30\, Krakow\, Mazowieckie\, Poland LOCATION:Room: H24\, Bldg: B1\, AGH University of Krakow\, Av. Mickiewicza 30\, Krakow\, Mazowieckie\, Poland ORGANIZER:kasinski@agh.edu.pl SEQUENCE:9 SUMMARY:Introduction to All-Digital Phase-Locked Loops (ADPLL) - Bogdan Sta szewski - SSCS Chapter Poland Seminar URL;VALUE=URI:https://events.vtools.ieee.org/m/450115 X-ALT-DESC:Description: <br /><div>Introduction to &ldquo\;All-Digital Phas e-Locked Loops (ADPLL)&rdquo\; - Bogdan Staszewski - SSCS Chapter Poland S eminar</div>\n<div>\n<p>AGH University of Krak&oacute\;w\, Lecture hall H- 24\, building B-1.</p>\n<p>&nbsp\;</p>\n<p>The past two decades has seen p roliferation of all-digital phase-locked loops (ADPLL) for RF and high-per formance frequency synthesis due to their clear benefits of flexibility\, reconfigurability\, transfer function precision\, settling speed\, frequen cy modulation capability\, and amenability to integration with digital bas eband and application processors. When implemented in nanoscale CMOS\, the ADPLL also exhibits advantages of better performance\, lower power consum ption\, lower area and cost over the traditional analog-intensive charge-p ump PLL. In a typical ADPLL\, a traditional VCO got directly replaced by a digitally controlled oscillator (DCO) for generating an output variable c lock\, a traditional phase/frequency detector and a charge pump got replac ed by a time-to-digital converter (TDC) for detecting phase departures of the variable clock versus the frequency reference (FREF) clock\, and an an alog loop RC filter got replaced with a digital loop filter. The conversio n gains of the DCO and TDC circuits are readily estimated and compensated using &ldquo\;free&rdquo\; but powerful digital logic.</p>\n</div> END:VEVENT END:VCALENDAR