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DESCRIPTION:Title: Interconnection Scaling – Going Big and Going Small\n\
 nAbstract: This presentation will cover a high-level overview of interconn
 ections between integrated circuits – trends over the past several decad
 es and what technologies may support future trends\, along with a discussi
 on of basic signal integrity considerations for such interconnections. Ove
 r most of the past 50 years the scaling of silicon integration was the win
 ning hand for increased performance with packaging and interconnections sc
 aling at substantially lower rates. Fundamental challenges in nanometer pr
 ocess nodes have effectively ended the steadily increasing benefits of Moo
 re’s Law so new paradigms for 2D\, 2.5D\, and 3D Heterogeneous Integrati
 on packaging technologies are being proposed and developed to keep system 
 performance scaling moving forward. Rapidly moving a lot of data between c
 hips is fundamental to all these approaches. One approach for dense\, high
  bandwidth interconnections will be discussed in some detail to illustrate
  tradeoffs and discuss the limits of how interconnections between chips ca
 n reach the limits of interconnections within chips.\n\nCo-sponsored by: U
 niversity of Colorado Boulder\n\nAgenda: \n6:30PM - 7:00PM Social\n7:00PM 
 - 8:00PM Technical Talk\n\nRoom: KOBL 352\, Bldg: Rustandy Building\, 1111
  Engineering Dr\, Boulder\, Colorado\, United States\, 80309
LOCATION:Room: KOBL 352\, Bldg: Rustandy Building\, 1111 Engineering Dr\, B
 oulder\, Colorado\, United States\, 80309
ORGANIZER:gowansj@ieee.org
SEQUENCE:23
SUMMARY:CIS & CIR\, EMC\, and CU Boulder: Interconnection Scaling – Going
  Big and Going Small
URL;VALUE=URI:https://events.vtools.ieee.org/m/465158
X-ALT-DESC:Description: <br /><p><strong>Title:&nbsp\;</strong>Interconnect
 ion Scaling &ndash\; Going Big and Going Small</p>\n<p><strong>Abstract: <
 /strong>This presentation will cover a high-level overview of interconnect
 ions between integrated circuits &ndash\; trends over the past several dec
 ades and what technologies may support future trends\, along with a discus
 sion of basic signal integrity considerations for such interconnections. O
 ver most of the past 50 years the scaling of silicon integration was the w
 inning hand for increased performance with packaging and interconnections 
 scaling at substantially lower rates. Fundamental challenges in nanometer 
 process nodes have effectively ended the steadily increasing benefits of M
 oore&rsquo\;s Law so new paradigms for 2D\, 2.5D\, and 3D Heterogeneous In
 tegration packaging technologies are being proposed and developed to keep 
 system performance scaling moving forward. Rapidly moving a lot of data be
 tween chips is fundamental to all these approaches. One approach for dense
 \, high bandwidth interconnections will be discussed in some detail to ill
 ustrate tradeoffs and discuss the limits of how interconnections between c
 hips can reach the limits of interconnections within chips.</p><br /><br /
 >Agenda: <br /><div class="abstract">6:30PM - 7:00PM Social</div>\n<div cl
 ass="abstract">7:00PM - 8:00PM Technical Talk</div>\n<p>&nbsp\;</p>
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