BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:US/Pacific BEGIN:DAYLIGHT DTSTART:20250309T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20241103T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250225T181438Z UID:E82F7274-EEAC-4DB9-95FA-8A4F10C5BF24 DTSTART;TZID=US/Pacific:20250225T090000 DTEND;TZID=US/Pacific:20250225T100000 DESCRIPTION:IEEE SSCS Oregon Chapter February Meeting and Seminar\n\nJoin u s for a talk from SSCS Distinguished Lecturer Prof. Shanthi Pavan from IIT Madras on Tuesday\, February 25th\, 2025. The seminar will be held from 9 :00am to 10:00am (PST) via a Hybrid format. Please register for the meetin g link and information.\n\nTopic:\n\nContinuous-Time Pipelined Analog-to-D igital Converters - Where Filtering Meets Analog-to-Digital Conversion\n\n Abstract:\n\nIf someone told you that the power\, noise\, distortion\, and area of a mixed-signal block could be reduced simultaneously\, you'd prob ably think this was a lie. It turns out that it is indeed possible sometim es - and this talk will present an example called the continuous-time pipe line (CTP) ADC. The CTP is an emerging technique that combines filtering w ith analog-to-digital conversion. Like a continuous-time delta-sigma modul ator (CTDSM)\, a CTP has a "nice" input impedance that is easy to drive an d has inherent anti-aliasing. However\, unlike a CTDSM\, a CTP does not re quire a high-speed feedback loop to be closed. As a result\, it can achiev e significantly higher bandwidth (like a Nyquist ADC). After discussing th e operating principles behind the CTP\, we describe the fundamental benefi ts of the CTP over a conventional signal chain that incorporates an anti-a lias filter and a Nyquist-rate converter. We will then show design details and measurement results from a 12-bit ENOB\, 100MHz 800MS/s CTP designed in a 65nm CMOS process.\n\nSpeaker Biography:\n\nShanthi Pavan received th e B.Tech. degree in electronics and communication engineering from IIT Mad ras\, Chennai\, India\, in 1995\, and the M.S. and D.Sc. degrees from Colu mbia University\, New York\, NY\, USA\, in 1997 and 1999\, respectively. F rom 1997 to 2000\, he was with Texas Instruments\, Warren\, NJ\, USA\, whe re he worked on high-speed analog filters and data converters. From 2000 t o June 2002\, he worked on microwave ICs for data communication at Bigbear Networks\, Sunnyvale\, CA\, USA. Since July 2002\, he has been with IIT M adras\, where he is currently the NT Alexander Institute Chair Professor o f Electrical Engineering. Prof. Pavan is the author of Understanding Delta -Sigma Data Converters (second edition\, with Richard Schreier and Gabor T emes)\, which received the Wiley-IEEE Press Professional Book Award for th e year 2020. His research interests are in the areas of high-speed analog circuit design and signal processing. Dr. Pavan is a fellow of the Indian National Academy of Engineering\, and the Indian National Science Academy\ , and the recipient of several awards\, including the IEEE Circuits and Sy stems Society Darlington Best Paper Award in 2009. He has served as the Ed itor-in-Chief of the IEEE Transactions on Circuits and Systems—I: Regula r Papers and on the Technical Program Committee of the International Solid -State Circuits Conference (ISSCC). He has served as a Distinguished Lectu rer of the IEEE Circuits and Systems Society and is a two-term Distinguish ed Lecturer of the Solid-State Circuits Society. He currently serves as th e Vice-President of Publications of the IEEE Solid-State Circuits Society and on the editorial board of the IEEE Journal of Solid-State Circuits. He is an IEEE Fellow.\n\nSpeaker(s): Prof. Shanthi Pavan\n\nAgenda: \n9:00am - 10:00am: Professional/Career Seminar\n\nRoom: JFCC-119\, Bldg: Jones Fa rm Conference Center\, 2111 NE 25th Ave\, Hillsboro\, Oregon\, United Sta tes\, 97124\, Virtual: https://events.vtools.ieee.org/m/467173 LOCATION:Room: JFCC-119\, Bldg: Jones Farm Conference Center\, 2111 NE 25t h Ave\, Hillsboro\, Oregon\, United States\, 97124\, Virtual: https://even ts.vtools.ieee.org/m/467173 ORGANIZER:rdorrance@ieee.org SEQUENCE:17 SUMMARY:IEEE SSCS Oregon Chapter February Meeting and Seminar (Hybrid) URL;VALUE=URI:https://events.vtools.ieee.org/m/467173 X-ALT-DESC:Description: <br /><p><span style="text-decoration: underline\; color: #000000\;">IEEE SSCS Oregon Chapter February Meeting and Seminar</s pan></p>\n<p><span style="color: #000000\;">Join us for a talk from SSCS D istinguished Lecturer Prof. Shanthi Pavan from IIT Madras on Tuesday\, Feb ruary 25th\, 2025. The seminar will be held from 9:00am to 10:00am (PST) v ia a Hybrid format. Please register for the meeting link and information.< /span></p>\n<p>&nbsp\;</p>\n<p><span style="color: #000000\;">Topic:</span ></p>\n<p>Continuous-Time Pipelined Analog-to-Digital Converters - Where F iltering Meets Analog-to-Digital Conversion</p>\n<p>&nbsp\;</p>\n<p><span style="color: #000000\;">Abstract:</span></p>\n<p>If someone told you that the power\, noise\, distortion\, and area of a mixed-signal block could b e reduced simultaneously\, you'd probably think this was a lie. It turns o ut that it is indeed possible sometimes - and this talk will present an ex ample called the continuous-time pipeline (CTP) ADC. The CTP is an emergin g technique that combines filtering with analog-to-digital conversion. Lik e a continuous-time delta-sigma modulator (CTDSM)\, a CTP has a "nice" inp ut impedance that is easy to drive and has inherent anti-aliasing. However \, unlike a CTDSM\, a CTP does not require a high-speed feedback loop to b e closed. As a result\, it can achieve significantly higher bandwidth (lik e a Nyquist ADC). After discussing the operating principles behind the CTP \, we describe the fundamental benefits of the CTP over a conventional sig nal chain that incorporates an anti-alias filter and a Nyquist-rate conver ter. We will then show design details and measurement results from a 12-bi t ENOB\, 100MHz 800MS/s CTP designed in a 65nm CMOS process.</p>\n<p>&nbsp \;</p>\n<p><span style="color: #000000\;">Speaker Biography:</span></p>\n< p>Shanthi Pavan received the B.Tech. degree in electronics and communicati on engineering from IIT Madras\, Chennai\, India\, in 1995\, and the M.S. and D.Sc. degrees from Columbia University\, New York\, NY\, USA\, in 1997 and 1999\, respectively. From 1997 to 2000\, he was with Texas Instrument s\, Warren\, NJ\, USA\, where he worked on high-speed analog filters and d ata converters. From 2000 to June 2002\, he worked on microwave ICs for da ta communication at Bigbear Networks\, Sunnyvale\, CA\, USA. Since July 20 02\, he has been with IIT Madras\, where he is currently the NT Alexander Institute Chair Professor of Electrical Engineering. Prof. Pavan is the au thor of Understanding Delta-Sigma Data Converters (second edition\, with R ichard Schreier and Gabor Temes)\, which received the Wiley-IEEE Press Pro fessional Book Award for the year 2020. His research interests are in the areas of high-speed analog circuit design and signal processing. Dr. Pavan is a fellow of the Indian National Academy of Engineering\, and the India n National Science Academy\, and the recipient of several awards\, includi ng the IEEE Circuits and Systems Society Darlington Best Paper Award in 20 09. He has served as the Editor-in-Chief of the IEEE Transactions on Circu its and Systems&mdash\;I: Regular Papers and on the Technical Program Comm ittee of the International Solid-State Circuits Conference (ISSCC). He has served as a Distinguished Lecturer of the IEEE Circuits and Systems Socie ty and is a two-term Distinguished Lecturer of the Solid-State Circuits So ciety. He currently serves as the Vice-President of Publications of the IE EE Solid-State Circuits Society and on the editorial board of the IEEE Jou rnal of Solid-State Circuits. He is an IEEE Fellow.</p><br /><br />Agenda: <br /><p>9:00am - 10:00am: Professional/Career Seminar</p> END:VEVENT END:VCALENDAR